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llvm-project
/
llvm
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test
/
Transforms
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InterleavedAccess
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Rajveer Singh Bharadwaj
5fd59466f2
[AArch64][SVE] Allow factors other than 2/4 for load+deinterleave3+store patterns for codegen (
#162475
)
...
Resolves
#159801
and
#162068
2025-10-16 20:44:01 +05:30
..
AArch64
[AArch64][SVE] Allow factors other than 2/4 for load+deinterleave3+store patterns for codegen (
#162475
)
2025-10-16 20:44:01 +05:30
ARM
…
RISCV
[RISCV] Cost bf16/f16 vector non-unit memory accesses as legal without zvfhmin/zvfbfmin (
#150882
)
2025-07-28 22:59:49 +08:00
X86
…
