shylie/llvm-project
1
0
Fork 0
Code Issues Pull Requests Actions 6 Packages Projects Releases Wiki Activity
llvm-project/llvm/lib/Target/RISCV
History
Craig Topper 1fab0ac559 [RISCV] Rename ReadVIALUCV->ReadVICALUV to match WriteVICALUV. NFC
2022-10-14 12:11:55 -07:00
..
AsmParser
[RISCV][CodeGen] add assertion to RISCVTargetStreamer getTargetStreamer()
2022-08-31 11:15:47 -07:00
Disassembler
Rename MCFixedLenDisassembler.h as MCDecoderOps.h
2022-05-15 08:44:58 +08:00
MCTargetDesc
[NFC][RISCV] Move getSEWLMULRatio function to header
2022-10-05 15:10:53 +01:00
TargetInfo
[RISCV] Re-enable JIT support
2022-08-11 11:41:02 +02:00
CMakeLists.txt
[RISCV] Add a RISCV specific CodeGenPrepare pass.
2022-07-14 10:20:59 -07:00
RISCV.h
[RISCV] Pre-RA expand pseudos pass
2022-07-31 23:19:00 +02:00
RISCV.td
[RISCV] Remove support for the unratified Zbe, Zbf, and Zbm extensions.
2022-09-22 13:04:41 -07:00
RISCVAsmPrinter.cpp
[RISC-V][HWASAN] Fold variable into assert
2022-08-29 00:32:37 +02:00
RISCVCallingConv.td
…
RISCVCallLowering.cpp
…
RISCVCallLowering.h
…
RISCVCodeGenPrepare.cpp
[RISCV] isImpliedByDomCondition returns an Optional<bool> not a bool.
2022-08-12 22:21:05 -07:00
RISCVExpandAtomicPseudoInsts.cpp
[RISCV] Avoid redundant branch-to-branch when expanding cmpxchg
2022-08-17 13:49:15 +01:00
RISCVExpandPseudoInsts.cpp
[RISCV] Pre-RA expand pseudos pass
2022-07-31 23:19:00 +02:00
RISCVFrameLowering.cpp
[RISCV] Pass the destination register to getVLENFactoredAmount instead of returning it. NFC
2022-10-03 10:59:35 -07:00
RISCVFrameLowering.h
[RISCV][NFCI] Set TransientStackAlignment and rely on it rather than RVV-specific logic on RVV-less functions
2022-08-02 09:46:06 +01:00
RISCVGatherScatterLowering.cpp
[RISCV] Extend strided load/store pattern matching to non-loop cases
2022-09-27 12:56:58 -07:00
RISCVInsertVSETVLI.cpp
[RISCV] Use mask/tail agnostic if tied source is IMPLICIT_DEF regardless of the policy operand.
2022-10-11 16:40:16 -07:00
RISCVInstrFormats.td
[RISCV] Support mask policy for RVV IR intrinsics.
2022-03-22 01:19:16 -07:00
RISCVInstrFormatsC.td
…
RISCVInstrFormatsV.td
…
RISCVInstrInfo.cpp
[RISCV] Verify that policy operands only exist on instructions with tied passthru operands
2022-10-06 15:18:43 -07:00
RISCVInstrInfo.h
[RISCV] Pass the destination register to getVLENFactoredAmount instead of returning it. NFC
2022-10-03 10:59:35 -07:00
RISCVInstrInfo.td
[RISCV] Use hasAllWUsers to recover XORI/ORI
2022-10-10 14:16:50 +08:00
RISCVInstrInfoA.td
[RISCV] Add target feature to force-enable atomics
2022-08-09 16:04:46 +02:00
RISCVInstrInfoC.td
[RISCV] : Add support for simm10_lsb0000nonzero operand.
2022-08-26 14:37:37 +08:00
RISCVInstrInfoD.td
[RISCV] Rename WriteFALU* and ReadFALU* to WriteFAdd*/ReadFAdd*.
2022-09-12 09:37:28 -07:00
RISCVInstrInfoF.td
[RISCV] Rename WriteFALU* and ReadFALU* to WriteFAdd*/ReadFAdd*.
2022-09-12 09:37:28 -07:00
RISCVInstrInfoM.td
[RISCV][Clang] Add support for Zmmul extension
2022-07-18 20:26:08 -04:00
RISCVInstrInfoV.td
[RISCV] Rename ReadVIALUCV->ReadVICALUV to match WriteVICALUV. NFC
2022-10-14 12:11:55 -07:00
RISCVInstrInfoVPseudos.td
[RISCV] Rename ReadVIALUCV->ReadVICALUV to match WriteVICALUV. NFC
2022-10-14 12:11:55 -07:00
RISCVInstrInfoVSDPatterns.td
[RISCV] Use _TIED form of VFWADD(U)_WV/VFWSUB(U)_WV to avoid early clobber.
2022-10-03 21:44:08 -07:00
RISCVInstrInfoVVLPatterns.td
[RISCV] Add isel patterns for vmacc, vnmsac.
2022-10-12 09:19:01 +08:00
RISCVInstrInfoZb.td
[RISCV] Add missing scheduler classes to Zbkb and Zbkx instructions.
2022-09-23 21:38:42 -07:00
RISCVInstrInfoZfh.td
[RISCV] Rename WriteFALU* and ReadFALU* to WriteFAdd*/ReadFAdd*.
2022-09-12 09:37:28 -07:00
RISCVInstrInfoZicbo.td
[RISCV][NFC] Fix typo in comment in RISCVInstrInfoZicbo.td
2022-09-01 13:49:55 +01:00
RISCVInstrInfoZk.td
…
RISCVInstructionSelector.cpp
…
RISCVISelDAGToDAG.cpp
[RISCV] Use hasAllWUsers to recover XORI/ORI
2022-10-10 14:16:50 +08:00
RISCVISelDAGToDAG.h
[RISCV] Support peephole optimization to fold vmerge.vvm that has tail agnostic policy and unmasked intrinsics.
2022-09-21 10:56:37 +08:00
RISCVISelLowering.cpp
[RISCV] Match (select C, -1, X)->(or -C, X) during lowerSelect
2022-10-13 09:06:12 -07:00
RISCVISelLowering.h
[RISCV] Disallow scale for scatter/gather
2022-09-22 15:31:26 -07:00
RISCVLegalizerInfo.cpp
…
RISCVLegalizerInfo.h
…
RISCVMachineFunctionInfo.cpp
[RISCV] Teach SExtWRemoval to recognize sign extended values that come from arguments.
2022-10-04 15:39:10 -07:00
RISCVMachineFunctionInfo.h
[RISCV] Teach SExtWRemoval to recognize sign extended values that come from arguments.
2022-10-04 15:39:10 -07:00
RISCVMacroFusion.cpp
[RISCV] Be more strict about LUI+ADDI macrofusion pre-RA.
2022-08-21 10:58:15 -07:00
RISCVMacroFusion.h
[RISCV] Add macrofusion infrastructure and one example usage.
2022-06-23 08:38:39 -07:00
RISCVMakeCompressible.cpp
[RISCV] Fix wrong register rename for store value during make-compressible optimization
2022-07-08 18:07:17 +08:00
RISCVMCInstLower.cpp
[RISCV] Pre-RA expand pseudos pass
2022-07-31 23:19:00 +02:00
RISCVMergeBaseOffset.cpp
[RISCV] Fix operand number in debug message in RISCVMergeBaseOffset.
2022-08-02 15:27:23 -07:00
RISCVRedundantCopyElimination.cpp
[RISCV] Use analyzeBranch in RISCVRedundantCopyElimination.
2022-08-29 09:05:53 -07:00
RISCVRegisterBankInfo.cpp
[Target] Apply clang-tidy fixes for readability-redundant-member-init (NFC)
2022-03-27 22:22:37 -07:00
RISCVRegisterBankInfo.h
[nfc][codegen] Move RegisterBank[Info].h under CodeGen
2022-03-01 21:53:25 -08:00
RISCVRegisterBanks.td
…
RISCVRegisterInfo.cpp
[RISCV] Refactor and improve eliminateFrameIndex.
2022-10-04 09:32:27 -07:00
RISCVRegisterInfo.h
[RegisterInfoEmitter] Generate isConstantPhysReg(). NFCI
2022-08-24 14:16:20 +00:00
RISCVRegisterInfo.td
[RegisterInfoEmitter] Generate isConstantPhysReg(). NFCI
2022-08-24 14:16:20 +00:00
RISCVSchedRocket.td
[RISCV] Add missing scheduler classes to Zbkb and Zbkx instructions.
2022-09-23 21:38:42 -07:00
RISCVSchedSiFive7.td
[RISCV] Add missing scheduler classes to Zbkb and Zbkx instructions.
2022-09-23 21:38:42 -07:00
RISCVSchedule.td
[RISCV] Rename RISCVScheduleB.td to RISCVScheduleZb.td. NFC
2022-09-23 21:38:42 -07:00
RISCVScheduleV.td
[RISCV] Rename ReadVIALUCV->ReadVICALUV to match WriteVICALUV. NFC
2022-10-14 12:11:55 -07:00
RISCVScheduleZb.td
[RISCV] Rename RISCVScheduleB.td to RISCVScheduleZb.td. NFC
2022-09-23 21:38:42 -07:00
RISCVSExtWRemoval.cpp
[RISCV] Teach SExtWRemoval to recognize sign extended values that come from arguments.
2022-10-04 15:39:10 -07:00
RISCVSubtarget.cpp
[RISCV] Enable fixed length vectors and loop vectorization with same
2022-08-26 14:45:23 -07:00
RISCVSubtarget.h
[RISCV] Remove support for the unratified Zbe, Zbf, and Zbm extensions.
2022-09-22 13:04:41 -07:00
RISCVSystemOperands.td
…
RISCVTargetMachine.cpp
[RISCV] Add the GlobalMerge pass (disabled by default)
2022-09-08 18:40:38 -07:00
RISCVTargetMachine.h
[llvm] Remove redundaunt virtual specifiers (NFC)
2022-07-24 21:50:35 -07:00
RISCVTargetObjectFile.cpp
…
RISCVTargetObjectFile.h
…
RISCVTargetTransformInfo.cpp
[RISCV] Correct RISCVTTIImpl::getRegUsageForType for vectors of pointers.
2022-10-14 11:34:12 -07:00
RISCVTargetTransformInfo.h
[RISCV] Rename getVectorImmCost to getStoreImmCost [nfc]
2022-09-27 08:22:13 -07:00