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llvm-project/llvm/test/CodeGen
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Kazu Hirata 8f1accfb35 Revert "[RISCV] Update the interface of sifive vqmaccqoq (#74284)" 
This reverts commit dc5570319676c14c48440b4ee87c8cfb35102ff6.

Several bots seem to be failing:

https://lab.llvm.org/buildbot/#/builders/10/builds/34651
https://lab.llvm.org/buildbot/#/builders/178/builds/6320
https://lab.llvm.org/buildbot/#/builders/77/builds/32918
2023-12-11 22:46:43 -08:00
..
AArch64
[AArch64]: Added code for generating XAR instruction (#75085)
2023-12-12 05:48:45 +00:00
AMDGPU
[GlobalISel] Add G_PREFETCH (#74863)
2023-12-11 11:06:50 +00:00
ARC
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ARM
[DAG] isSplatValue - node is a splat if all demanded elts have the same whole constant value (#74443)
2023-12-08 10:53:51 +00:00
AVR
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BPF
[BPF][GlobalISel] add initial gisel support for BPF (#74999)
2023-12-11 19:58:34 +08:00
CSKY
[CSKY,test] Update switch.ll
2023-10-31 15:47:05 -07:00
DirectX
[DirectX] Move ROV info into HLSL metadata. NFC
2023-12-09 10:42:45 -08:00
Generic
[CodeGen] Update DwarfEHPreparePass references in CodeGenPassBuilder.h (#74068)
2023-12-11 09:26:01 +08:00
Hexagon
[Tests] Add disjoint flag to some tests (NFC)
2023-12-05 14:09:36 +01:00
Inputs
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Lanai
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LoongArch
[LoongArch] Add codegen support for [X]VF{MSUB/NMADD/NMSUB}.{S/D} instructions (#74819)
2023-12-11 10:37:22 +08:00
M68k
[M68k] Emit RTE for interrupt handler. (#72787)
2023-12-04 15:11:00 +08:00
Mips
[CodeGen] Update DwarfEHPreparePass references in CodeGenPassBuilder.h (#74068)
2023-12-11 09:26:01 +08:00
MIR
MachineVerifier: Reject extra non-register operands on instructions (#73758)
2023-11-30 22:33:42 +09:00
MLRegAlloc
[mlgo] Fix test post PR #73899
2023-12-01 09:05:22 -08:00
MSP430
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NVPTX
[NVPTX] Custom lower integer<->bf16 conversions for sm_80 (#74827)
2023-12-11 21:06:46 +01:00
PowerPC
[MachinePipeliner] Fix store-store dependences (#72575)
2023-12-11 21:10:34 -06:00
RISCV
Revert "[RISCV] Update the interface of sifive vqmaccqoq (#74284)"
2023-12-11 22:46:43 -08:00
SPARC
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SPIRV
[SPIR-V] Fixup tests (#73371)
2023-12-07 15:23:27 -05:00
SystemZ
[SystemZ] Use LCGR/AGHI for i64 XOR with -1 (#74882)
2023-12-11 17:28:12 +01:00
Thumb
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Thumb2
[SCEVExpander] Attempt to reinfer flags dropped due to CSE (#72431)
2023-12-07 13:20:36 -08:00
VE
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WebAssembly
[CodeGen] Rename winehprepare -> win-eh-prepare (#75024)
2023-12-11 13:55:27 +08:00
WinCFGuard
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WinEH
[CodeGen] Rename winehprepare -> win-eh-prepare (#75024)
2023-12-11 13:55:27 +08:00
X86
[CodeGen] Port SelectOptimize to new pass manager (#74920)
2023-12-12 12:09:30 +08:00
XCore
[XCore] Set MaxAtomicSizeInBitsSupported to 0 (#74389)
2023-12-05 12:51:01 -05:00