b968fd9502
This switches them to use tho common TableGen layer, extending it to support the missing features needed by the NVPTX backend. The biggest thing was to build a TableGen system that computes the cumulative SM and PTX feature sets the same way the macros did. That's done with some string concatenation tricks in TableGen, but they worked out pretty neatly and are very comparable in complexity to the macro version. Then the actual defines were mapped over using a very hacky Python script. It was never productionized or intended to work in the future, but for posterity: https://gist.github.com/chandlerc/10bdf8fb1312e252b4a501bace184b66 Last but not least, there was a very odd "bug" in one of the converted builtins' prototype in the TableGen model: it didn't handle uses of `Z` and `U` both as *qualifiers* of a single type, treating `Z` as its own `int32_t` type. So my hacky Python script converted `ZUi` into two types, an `int32_t` and an `unsigned int`. This produced a very wrong prototype. But the tests caught this nicely and I fixed it manually rather than trying to improve the Python script as it occurred in exactly one place I could find. This should provide direct benefits of allowing future refactorings to more directly leverage TableGen to express builtins more structurally rather than textually. It will also make my efforts to move builtins to string tables significantly more effective for the NVPTX backend where the X-macro approach resulted in *significantly* less efficient string tables than other targets due to the long repeated feature strings.
301 lines
10 KiB
C++
301 lines
10 KiB
C++
//===--- NVPTX.cpp - Implement NVPTX target feature support ---------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements NVPTX TargetInfo objects.
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//
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//===----------------------------------------------------------------------===//
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#include "NVPTX.h"
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#include "Targets.h"
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#include "clang/Basic/Builtins.h"
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#include "clang/Basic/MacroBuilder.h"
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#include "clang/Basic/TargetBuiltins.h"
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#include "llvm/ADT/StringSwitch.h"
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using namespace clang;
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using namespace clang::targets;
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static constexpr Builtin::Info BuiltinInfo[] = {
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#define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \
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{#ID, TYPE, ATTRS, FEATURE, HeaderDesc::NO_HEADER, ALL_LANGUAGES},
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#include "clang/Basic/BuiltinsNVPTX.inc"
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};
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const char *const NVPTXTargetInfo::GCCRegNames[] = {"r0"};
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NVPTXTargetInfo::NVPTXTargetInfo(const llvm::Triple &Triple,
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const TargetOptions &Opts,
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unsigned TargetPointerWidth)
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: TargetInfo(Triple) {
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assert((TargetPointerWidth == 32 || TargetPointerWidth == 64) &&
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"NVPTX only supports 32- and 64-bit modes.");
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PTXVersion = 32;
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for (const StringRef Feature : Opts.FeaturesAsWritten) {
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int PTXV;
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if (!Feature.starts_with("+ptx") ||
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Feature.drop_front(4).getAsInteger(10, PTXV))
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continue;
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PTXVersion = PTXV; // TODO: should it be max(PTXVersion, PTXV)?
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}
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TLSSupported = false;
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VLASupported = false;
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AddrSpaceMap = &NVPTXAddrSpaceMap;
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UseAddrSpaceMapMangling = true;
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// __bf16 is always available as a load/store only type.
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BFloat16Width = BFloat16Align = 16;
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BFloat16Format = &llvm::APFloat::BFloat();
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// Define available target features
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// These must be defined in sorted order!
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NoAsmVariants = true;
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GPU = OffloadArch::UNUSED;
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// PTX supports f16 as a fundamental type.
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HasLegalHalfType = true;
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HasFloat16 = true;
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if (TargetPointerWidth == 32)
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resetDataLayout("e-p:32:32-i64:64-i128:128-v16:16-v32:32-n16:32:64");
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else if (Opts.NVPTXUseShortPointers)
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resetDataLayout(
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"e-p3:32:32-p4:32:32-p5:32:32-i64:64-i128:128-v16:16-v32:32-n16:32:64");
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else
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resetDataLayout("e-i64:64-i128:128-v16:16-v32:32-n16:32:64");
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// If possible, get a TargetInfo for our host triple, so we can match its
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// types.
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llvm::Triple HostTriple(Opts.HostTriple);
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if (!HostTriple.isNVPTX())
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HostTarget = AllocateTarget(llvm::Triple(Opts.HostTriple), Opts);
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// If no host target, make some guesses about the data layout and return.
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if (!HostTarget) {
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LongWidth = LongAlign = TargetPointerWidth;
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PointerWidth = PointerAlign = TargetPointerWidth;
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switch (TargetPointerWidth) {
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case 32:
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SizeType = TargetInfo::UnsignedInt;
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PtrDiffType = TargetInfo::SignedInt;
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IntPtrType = TargetInfo::SignedInt;
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break;
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case 64:
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SizeType = TargetInfo::UnsignedLong;
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PtrDiffType = TargetInfo::SignedLong;
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IntPtrType = TargetInfo::SignedLong;
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break;
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default:
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llvm_unreachable("TargetPointerWidth must be 32 or 64");
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}
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MaxAtomicInlineWidth = TargetPointerWidth;
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return;
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}
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// Copy properties from host target.
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PointerWidth = HostTarget->getPointerWidth(LangAS::Default);
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PointerAlign = HostTarget->getPointerAlign(LangAS::Default);
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BoolWidth = HostTarget->getBoolWidth();
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BoolAlign = HostTarget->getBoolAlign();
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IntWidth = HostTarget->getIntWidth();
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IntAlign = HostTarget->getIntAlign();
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HalfWidth = HostTarget->getHalfWidth();
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HalfAlign = HostTarget->getHalfAlign();
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FloatWidth = HostTarget->getFloatWidth();
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FloatAlign = HostTarget->getFloatAlign();
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DoubleWidth = HostTarget->getDoubleWidth();
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DoubleAlign = HostTarget->getDoubleAlign();
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LongWidth = HostTarget->getLongWidth();
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LongAlign = HostTarget->getLongAlign();
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LongLongWidth = HostTarget->getLongLongWidth();
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LongLongAlign = HostTarget->getLongLongAlign();
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MinGlobalAlign = HostTarget->getMinGlobalAlign(/* TypeSize = */ 0,
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/* HasNonWeakDef = */ true);
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NewAlign = HostTarget->getNewAlign();
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DefaultAlignForAttributeAligned =
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HostTarget->getDefaultAlignForAttributeAligned();
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SizeType = HostTarget->getSizeType();
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IntMaxType = HostTarget->getIntMaxType();
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PtrDiffType = HostTarget->getPtrDiffType(LangAS::Default);
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IntPtrType = HostTarget->getIntPtrType();
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WCharType = HostTarget->getWCharType();
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WIntType = HostTarget->getWIntType();
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Char16Type = HostTarget->getChar16Type();
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Char32Type = HostTarget->getChar32Type();
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Int64Type = HostTarget->getInt64Type();
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SigAtomicType = HostTarget->getSigAtomicType();
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ProcessIDType = HostTarget->getProcessIDType();
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UseBitFieldTypeAlignment = HostTarget->useBitFieldTypeAlignment();
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UseZeroLengthBitfieldAlignment = HostTarget->useZeroLengthBitfieldAlignment();
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UseExplicitBitFieldAlignment = HostTarget->useExplicitBitFieldAlignment();
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ZeroLengthBitfieldBoundary = HostTarget->getZeroLengthBitfieldBoundary();
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// This is a bit of a lie, but it controls __GCC_ATOMIC_XXX_LOCK_FREE, and
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// we need those macros to be identical on host and device, because (among
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// other things) they affect which standard library classes are defined, and
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// we need all classes to be defined on both the host and device.
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MaxAtomicInlineWidth = HostTarget->getMaxAtomicInlineWidth();
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// Properties intentionally not copied from host:
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// - LargeArrayMinWidth, LargeArrayAlign: Not visible across the
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// host/device boundary.
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// - SuitableAlign: Not visible across the host/device boundary, and may
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// correctly be different on host/device, e.g. if host has wider vector
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// types than device.
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// - LongDoubleWidth, LongDoubleAlign: nvptx's long double type is the same
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// as its double type, but that's not necessarily true on the host.
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// TODO: nvcc emits a warning when using long double on device; we should
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// do the same.
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}
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ArrayRef<const char *> NVPTXTargetInfo::getGCCRegNames() const {
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return llvm::ArrayRef(GCCRegNames);
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}
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bool NVPTXTargetInfo::hasFeature(StringRef Feature) const {
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return llvm::StringSwitch<bool>(Feature)
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.Cases("ptx", "nvptx", true)
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.Default(false);
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}
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void NVPTXTargetInfo::getTargetDefines(const LangOptions &Opts,
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MacroBuilder &Builder) const {
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Builder.defineMacro("__PTX__");
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Builder.defineMacro("__NVPTX__");
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// Skip setting architecture dependent macros if undefined.
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if (GPU == OffloadArch::UNUSED && !HostTarget)
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return;
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if (Opts.CUDAIsDevice || Opts.OpenMPIsTargetDevice || !HostTarget) {
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// Set __CUDA_ARCH__ for the GPU specified.
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std::string CUDAArchCode = [this] {
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switch (GPU) {
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case OffloadArch::GFX600:
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case OffloadArch::GFX601:
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case OffloadArch::GFX602:
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case OffloadArch::GFX700:
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case OffloadArch::GFX701:
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case OffloadArch::GFX702:
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case OffloadArch::GFX703:
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case OffloadArch::GFX704:
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case OffloadArch::GFX705:
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case OffloadArch::GFX801:
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case OffloadArch::GFX802:
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case OffloadArch::GFX803:
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case OffloadArch::GFX805:
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case OffloadArch::GFX810:
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case OffloadArch::GFX9_GENERIC:
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case OffloadArch::GFX900:
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case OffloadArch::GFX902:
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case OffloadArch::GFX904:
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case OffloadArch::GFX906:
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case OffloadArch::GFX908:
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case OffloadArch::GFX909:
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case OffloadArch::GFX90a:
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case OffloadArch::GFX90c:
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case OffloadArch::GFX9_4_GENERIC:
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case OffloadArch::GFX940:
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case OffloadArch::GFX941:
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case OffloadArch::GFX942:
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case OffloadArch::GFX950:
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case OffloadArch::GFX10_1_GENERIC:
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case OffloadArch::GFX1010:
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case OffloadArch::GFX1011:
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case OffloadArch::GFX1012:
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case OffloadArch::GFX1013:
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case OffloadArch::GFX10_3_GENERIC:
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case OffloadArch::GFX1030:
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case OffloadArch::GFX1031:
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case OffloadArch::GFX1032:
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case OffloadArch::GFX1033:
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case OffloadArch::GFX1034:
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case OffloadArch::GFX1035:
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case OffloadArch::GFX1036:
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case OffloadArch::GFX11_GENERIC:
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case OffloadArch::GFX1100:
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case OffloadArch::GFX1101:
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case OffloadArch::GFX1102:
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case OffloadArch::GFX1103:
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case OffloadArch::GFX1150:
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case OffloadArch::GFX1151:
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case OffloadArch::GFX1152:
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case OffloadArch::GFX1153:
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case OffloadArch::GFX12_GENERIC:
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case OffloadArch::GFX1200:
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case OffloadArch::GFX1201:
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case OffloadArch::AMDGCNSPIRV:
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case OffloadArch::Generic:
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case OffloadArch::LAST:
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break;
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case OffloadArch::UNKNOWN:
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assert(false && "No GPU arch when compiling CUDA device code.");
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return "";
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case OffloadArch::UNUSED:
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case OffloadArch::SM_20:
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return "200";
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case OffloadArch::SM_21:
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return "210";
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case OffloadArch::SM_30:
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return "300";
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case OffloadArch::SM_32_:
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return "320";
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case OffloadArch::SM_35:
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return "350";
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case OffloadArch::SM_37:
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return "370";
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case OffloadArch::SM_50:
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return "500";
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case OffloadArch::SM_52:
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return "520";
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case OffloadArch::SM_53:
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return "530";
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case OffloadArch::SM_60:
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return "600";
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case OffloadArch::SM_61:
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return "610";
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case OffloadArch::SM_62:
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return "620";
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case OffloadArch::SM_70:
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return "700";
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case OffloadArch::SM_72:
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return "720";
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case OffloadArch::SM_75:
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return "750";
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case OffloadArch::SM_80:
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return "800";
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case OffloadArch::SM_86:
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return "860";
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case OffloadArch::SM_87:
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return "870";
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case OffloadArch::SM_89:
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return "890";
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case OffloadArch::SM_90:
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case OffloadArch::SM_90a:
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return "900";
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case OffloadArch::SM_100:
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case OffloadArch::SM_100a:
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return "1000";
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}
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llvm_unreachable("unhandled OffloadArch");
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}();
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Builder.defineMacro("__CUDA_ARCH__", CUDAArchCode);
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if (GPU == OffloadArch::SM_90a)
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Builder.defineMacro("__CUDA_ARCH_FEAT_SM90_ALL", "1");
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if (GPU == OffloadArch::SM_100a)
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Builder.defineMacro("__CUDA_ARCH_FEAT_SM100_ALL", "1");
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}
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}
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ArrayRef<Builtin::Info> NVPTXTargetInfo::getTargetBuiltins() const {
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return llvm::ArrayRef(BuiltinInfo,
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clang::NVPTX::LastTSBuiltin - Builtin::FirstTSBuiltin);
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}
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