0288d065ee
If linker relaxation enabled, relaxable code sequence expanded from
pseudos should avoid being separated by instruction scheduling. This
commit tags scheduling boundary for them to avoid being scheduled.
(Except for `tls_le/tls_ie` and `call36/tail36`. Because `tls_le/tls_ie`
can be scheduled and have no influence to relax, `call36/tail36` are
expanded later in `LoongArchExpandPseudo` pass.)
A new mask target-flag is added to attach relax relocs to the relaxable
code sequence. (No need to add it for `tls_le` and `call36/tail36`
because we can simply add relax relocs for them according to their
relocs. But for other code sequence, such as `PCALA_{HI20/LO12}`, we
must use the mask flag, mainly because relax should not be added when
code model is large.)
Because of the new mask target-flag, get "direct" flags is necessary
when using their target-flags. In addition, code sequence after being
optimized by `MergeBaseOffset` pass may not relaxable any more, so the
relax "bitmask" flag should be removed.
195 lines
6.5 KiB
C++
195 lines
6.5 KiB
C++
//=- LoongArchMCInstLower.cpp - Convert LoongArch MachineInstr to an MCInst -=//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains code to lower LoongArch MachineInstrs to their
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// corresponding MCInst records.
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//
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//===----------------------------------------------------------------------===//
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#include "LoongArch.h"
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#include "MCTargetDesc/LoongArchBaseInfo.h"
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#include "MCTargetDesc/LoongArchMCExpr.h"
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#include "llvm/CodeGen/AsmPrinter.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/MC/MCAsmInfo.h"
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#include "llvm/MC/MCContext.h"
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using namespace llvm;
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static MCOperand lowerSymbolOperand(const MachineOperand &MO, MCSymbol *Sym,
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const AsmPrinter &AP) {
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MCContext &Ctx = AP.OutContext;
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LoongArchMCExpr::VariantKind Kind;
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switch (LoongArchII::getDirectFlags(MO)) {
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default:
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llvm_unreachable("Unknown target flag on GV operand");
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case LoongArchII::MO_None:
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Kind = LoongArchMCExpr::VK_LoongArch_None;
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break;
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case LoongArchII::MO_CALL:
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Kind = LoongArchMCExpr::VK_LoongArch_CALL;
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break;
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case LoongArchII::MO_CALL_PLT:
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Kind = LoongArchMCExpr::VK_LoongArch_CALL_PLT;
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break;
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case LoongArchII::MO_PCREL_HI:
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Kind = LoongArchMCExpr::VK_LoongArch_PCALA_HI20;
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break;
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case LoongArchII::MO_PCREL_LO:
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Kind = LoongArchMCExpr::VK_LoongArch_PCALA_LO12;
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break;
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case LoongArchII::MO_PCREL64_LO:
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Kind = LoongArchMCExpr::VK_LoongArch_PCALA64_LO20;
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break;
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case LoongArchII::MO_PCREL64_HI:
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Kind = LoongArchMCExpr::VK_LoongArch_PCALA64_HI12;
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break;
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case LoongArchII::MO_GOT_PC_HI:
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Kind = LoongArchMCExpr::VK_LoongArch_GOT_PC_HI20;
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break;
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case LoongArchII::MO_GOT_PC_LO:
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Kind = LoongArchMCExpr::VK_LoongArch_GOT_PC_LO12;
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break;
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case LoongArchII::MO_GOT_PC64_LO:
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Kind = LoongArchMCExpr::VK_LoongArch_GOT64_PC_LO20;
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break;
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case LoongArchII::MO_GOT_PC64_HI:
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Kind = LoongArchMCExpr::VK_LoongArch_GOT64_PC_HI12;
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break;
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case LoongArchII::MO_LE_HI:
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Kind = LoongArchMCExpr::VK_LoongArch_TLS_LE_HI20;
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break;
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case LoongArchII::MO_LE_LO:
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Kind = LoongArchMCExpr::VK_LoongArch_TLS_LE_LO12;
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break;
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case LoongArchII::MO_LE64_LO:
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Kind = LoongArchMCExpr::VK_LoongArch_TLS_LE64_LO20;
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break;
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case LoongArchII::MO_LE64_HI:
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Kind = LoongArchMCExpr::VK_LoongArch_TLS_LE64_HI12;
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break;
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case LoongArchII::MO_IE_PC_HI:
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Kind = LoongArchMCExpr::VK_LoongArch_TLS_IE_PC_HI20;
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break;
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case LoongArchII::MO_IE_PC_LO:
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Kind = LoongArchMCExpr::VK_LoongArch_TLS_IE_PC_LO12;
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break;
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case LoongArchII::MO_IE_PC64_LO:
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Kind = LoongArchMCExpr::VK_LoongArch_TLS_IE64_PC_LO20;
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break;
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case LoongArchII::MO_IE_PC64_HI:
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Kind = LoongArchMCExpr::VK_LoongArch_TLS_IE64_PC_HI12;
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break;
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case LoongArchII::MO_LD_PC_HI:
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Kind = LoongArchMCExpr::VK_LoongArch_TLS_LD_PC_HI20;
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break;
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case LoongArchII::MO_GD_PC_HI:
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Kind = LoongArchMCExpr::VK_LoongArch_TLS_GD_PC_HI20;
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break;
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case LoongArchII::MO_CALL36:
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Kind = LoongArchMCExpr::VK_LoongArch_CALL36;
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break;
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case LoongArchII::MO_DESC_PC_HI:
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Kind = LoongArchMCExpr::VK_LoongArch_TLS_DESC_PC_HI20;
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break;
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case LoongArchII::MO_DESC_PC_LO:
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Kind = LoongArchMCExpr::VK_LoongArch_TLS_DESC_PC_LO12;
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break;
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case LoongArchII::MO_DESC64_PC_LO:
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Kind = LoongArchMCExpr::VK_LoongArch_TLS_DESC64_PC_LO20;
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break;
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case LoongArchII::MO_DESC64_PC_HI:
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Kind = LoongArchMCExpr::VK_LoongArch_TLS_DESC64_PC_HI12;
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break;
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case LoongArchII::MO_DESC_LD:
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Kind = LoongArchMCExpr::VK_LoongArch_TLS_DESC_LD;
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break;
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case LoongArchII::MO_DESC_CALL:
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Kind = LoongArchMCExpr::VK_LoongArch_TLS_DESC_CALL;
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break;
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case LoongArchII::MO_LE_HI_R:
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Kind = LoongArchMCExpr::VK_LoongArch_TLS_LE_HI20_R;
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break;
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case LoongArchII::MO_LE_ADD_R:
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Kind = LoongArchMCExpr::VK_LoongArch_TLS_LE_ADD_R;
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break;
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case LoongArchII::MO_LE_LO_R:
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Kind = LoongArchMCExpr::VK_LoongArch_TLS_LE_LO12_R;
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break;
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// TODO: Handle more target-flags.
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}
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const MCExpr *ME =
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MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_None, Ctx);
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if (!MO.isJTI() && !MO.isMBB() && MO.getOffset())
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ME = MCBinaryExpr::createAdd(
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ME, MCConstantExpr::create(MO.getOffset(), Ctx), Ctx);
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if (Kind != LoongArchMCExpr::VK_LoongArch_None)
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ME = LoongArchMCExpr::create(ME, Kind, Ctx, LoongArchII::hasRelaxFlag(MO));
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return MCOperand::createExpr(ME);
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}
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bool llvm::lowerLoongArchMachineOperandToMCOperand(const MachineOperand &MO,
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MCOperand &MCOp,
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const AsmPrinter &AP) {
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switch (MO.getType()) {
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default:
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report_fatal_error(
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"lowerLoongArchMachineOperandToMCOperand: unknown operand type");
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case MachineOperand::MO_Register:
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// Ignore all implicit register operands.
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if (MO.isImplicit())
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return false;
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MCOp = MCOperand::createReg(MO.getReg());
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break;
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case MachineOperand::MO_RegisterMask:
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// Regmasks are like implicit defs.
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return false;
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case MachineOperand::MO_Immediate:
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MCOp = MCOperand::createImm(MO.getImm());
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break;
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case MachineOperand::MO_ConstantPoolIndex:
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MCOp = lowerSymbolOperand(MO, AP.GetCPISymbol(MO.getIndex()), AP);
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break;
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case MachineOperand::MO_GlobalAddress:
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MCOp = lowerSymbolOperand(MO, AP.getSymbolPreferLocal(*MO.getGlobal()), AP);
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break;
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case MachineOperand::MO_MachineBasicBlock:
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MCOp = lowerSymbolOperand(MO, MO.getMBB()->getSymbol(), AP);
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break;
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case MachineOperand::MO_ExternalSymbol:
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MCOp = lowerSymbolOperand(
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MO, AP.GetExternalSymbolSymbol(MO.getSymbolName()), AP);
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break;
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case MachineOperand::MO_BlockAddress:
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MCOp = lowerSymbolOperand(
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MO, AP.GetBlockAddressSymbol(MO.getBlockAddress()), AP);
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break;
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case MachineOperand::MO_JumpTableIndex:
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MCOp = lowerSymbolOperand(MO, AP.GetJTISymbol(MO.getIndex()), AP);
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break;
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}
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return true;
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}
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bool llvm::lowerLoongArchMachineInstrToMCInst(const MachineInstr *MI,
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MCInst &OutMI, AsmPrinter &AP) {
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OutMI.setOpcode(MI->getOpcode());
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for (const MachineOperand &MO : MI->operands()) {
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MCOperand MCOp;
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if (lowerLoongArchMachineOperandToMCOperand(MO, MCOp, AP))
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OutMI.addOperand(MCOp);
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}
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return false;
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}
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