ca4886bf96
Inspired by https://reviews.llvm.org/D146600, this commit adds some TTI hooks for LoongArch to make LoopDataPrefetch pass really work. Including: - `getCacheLineSize()`: 64 for loongarch64. - `getPrefetchDistance()`: After testing SPEC CPU 2017, improvements taken by prefetching are more obvious when set PrefetchDistance to 200(results shown blow), although different benchmarks fit for different best choice. - `enableWritePrefetching()`: store prefetch is supported by LoongArch, so set WritePrefetching to true in default. - `getMinPrefetchStride()` and `getMaxPrefetchIterationsAhead()` still use default values: 1 and UINT_MAX, so not override them. After this commit, the test added by https://reviews.llvm.org/D146600 can generate llvm.prefetch intrinsic IR correctly. Results of spec2017rate benchmarks (testing date: ref, copies: 1): - For all C/C++ benchmarks, compared to O3+novec/lsx/lasx, prefetch can bring about -1.58%/0.31%/0.07% performance improvement for int benchmarks and 3.26%/3.73%/3.78% improvement for floating point benchmarks. (Only O3+novec+prefetch decreases when testing intrate.) - But prefetch results in performance reduction almost for every Fortran benchmark compiled by flang. While considering all C/C++/Fortran benchmarks, prefetch performance will decrease about 1% ~ 5%. FIXME: Keep `loongarch-enable-loop-data-prefetch` option default to false for now due to the bad effect for Fortran.
99 lines
3.3 KiB
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99 lines
3.3 KiB
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//===-- LoongArchTargetTransformInfo.cpp - LoongArch specific TTI ---------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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/// \file
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/// This file implements a TargetTransformInfo analysis pass specific to the
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/// LoongArch target machine. It uses the target's detailed information to
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/// provide more precise answers to certain TTI queries, while letting the
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/// target independent and default TTI implementations handle the rest.
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///
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//===----------------------------------------------------------------------===//
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#include "LoongArchTargetTransformInfo.h"
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using namespace llvm;
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#define DEBUG_TYPE "loongarchtti"
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TypeSize LoongArchTTIImpl::getRegisterBitWidth(
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TargetTransformInfo::RegisterKind K) const {
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TypeSize DefSize = TargetTransformInfoImplBase::getRegisterBitWidth(K);
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switch (K) {
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case TargetTransformInfo::RGK_Scalar:
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return TypeSize::getFixed(ST->is64Bit() ? 64 : 32);
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case TargetTransformInfo::RGK_FixedWidthVector:
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if (ST->hasExtLASX())
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return TypeSize::getFixed(256);
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if (ST->hasExtLSX())
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return TypeSize::getFixed(128);
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[[fallthrough]];
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case TargetTransformInfo::RGK_ScalableVector:
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return DefSize;
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}
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llvm_unreachable("Unsupported register kind");
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}
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unsigned LoongArchTTIImpl::getNumberOfRegisters(unsigned ClassID) const {
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switch (ClassID) {
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case LoongArchRegisterClass::GPRRC:
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// 30 = 32 GPRs - r0 (zero register) - r21 (non-allocatable)
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return 30;
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case LoongArchRegisterClass::FPRRC:
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return ST->hasBasicF() ? 32 : 0;
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case LoongArchRegisterClass::VRRC:
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return ST->hasExtLSX() ? 32 : 0;
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}
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llvm_unreachable("unknown register class");
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}
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unsigned LoongArchTTIImpl::getRegisterClassForType(bool Vector,
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Type *Ty) const {
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if (Vector)
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return LoongArchRegisterClass::VRRC;
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if (!Ty)
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return LoongArchRegisterClass::GPRRC;
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Type *ScalarTy = Ty->getScalarType();
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if ((ScalarTy->isFloatTy() && ST->hasBasicF()) ||
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(ScalarTy->isDoubleTy() && ST->hasBasicD())) {
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return LoongArchRegisterClass::FPRRC;
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}
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return LoongArchRegisterClass::GPRRC;
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}
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unsigned LoongArchTTIImpl::getMaxInterleaveFactor(ElementCount VF) {
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return ST->getMaxInterleaveFactor();
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}
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const char *LoongArchTTIImpl::getRegisterClassName(unsigned ClassID) const {
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switch (ClassID) {
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case LoongArchRegisterClass::GPRRC:
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return "LoongArch::GPRRC";
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case LoongArchRegisterClass::FPRRC:
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return "LoongArch::FPRRC";
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case LoongArchRegisterClass::VRRC:
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return "LoongArch::VRRC";
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}
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llvm_unreachable("unknown register class");
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}
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TargetTransformInfo::PopcntSupportKind
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LoongArchTTIImpl::getPopcntSupport(unsigned TyWidth) {
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assert(isPowerOf2_32(TyWidth) && "Ty width must be power of 2");
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return ST->hasExtLSX() ? TTI::PSK_FastHardware : TTI::PSK_Software;
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}
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unsigned LoongArchTTIImpl::getCacheLineSize() const { return 64; }
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unsigned LoongArchTTIImpl::getPrefetchDistance() const { return 200; }
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bool LoongArchTTIImpl::enableWritePrefetching() const { return true; }
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// TODO: Implement more hooks to provide TTI machinery for LoongArch.
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