ca4886bf96
Inspired by https://reviews.llvm.org/D146600, this commit adds some TTI hooks for LoongArch to make LoopDataPrefetch pass really work. Including: - `getCacheLineSize()`: 64 for loongarch64. - `getPrefetchDistance()`: After testing SPEC CPU 2017, improvements taken by prefetching are more obvious when set PrefetchDistance to 200(results shown blow), although different benchmarks fit for different best choice. - `enableWritePrefetching()`: store prefetch is supported by LoongArch, so set WritePrefetching to true in default. - `getMinPrefetchStride()` and `getMaxPrefetchIterationsAhead()` still use default values: 1 and UINT_MAX, so not override them. After this commit, the test added by https://reviews.llvm.org/D146600 can generate llvm.prefetch intrinsic IR correctly. Results of spec2017rate benchmarks (testing date: ref, copies: 1): - For all C/C++ benchmarks, compared to O3+novec/lsx/lasx, prefetch can bring about -1.58%/0.31%/0.07% performance improvement for int benchmarks and 3.26%/3.73%/3.78% improvement for floating point benchmarks. (Only O3+novec+prefetch decreases when testing intrate.) - But prefetch results in performance reduction almost for every Fortran benchmark compiled by flang. While considering all C/C++/Fortran benchmarks, prefetch performance will decrease about 1% ~ 5%. FIXME: Keep `loongarch-enable-loop-data-prefetch` option default to false for now due to the bad effect for Fortran.
60 lines
2.3 KiB
C++
60 lines
2.3 KiB
C++
//===- LoongArchTargetTransformInfo.h - LoongArch specific TTI --*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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/// \file
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/// This file a TargetTransformInfo::Concept conforming object specific to the
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/// LoongArch target machine. It uses the target's detailed information to
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/// provide more precise answers to certain TTI queries, while letting the
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/// target independent and default TTI implementations handle the rest.
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///
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_LOONGARCH_LOONGARCHTARGETTRANSFORMINFO_H
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#define LLVM_LIB_TARGET_LOONGARCH_LOONGARCHTARGETTRANSFORMINFO_H
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#include "LoongArchSubtarget.h"
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#include "LoongArchTargetMachine.h"
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#include "llvm/Analysis/TargetTransformInfo.h"
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#include "llvm/CodeGen/BasicTTIImpl.h"
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namespace llvm {
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class LoongArchTTIImpl : public BasicTTIImplBase<LoongArchTTIImpl> {
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typedef BasicTTIImplBase<LoongArchTTIImpl> BaseT;
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typedef TargetTransformInfo TTI;
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friend BaseT;
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enum LoongArchRegisterClass { GPRRC, FPRRC, VRRC };
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const LoongArchSubtarget *ST;
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const LoongArchTargetLowering *TLI;
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const LoongArchSubtarget *getST() const { return ST; }
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const LoongArchTargetLowering *getTLI() const { return TLI; }
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public:
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explicit LoongArchTTIImpl(const LoongArchTargetMachine *TM, const Function &F)
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: BaseT(TM, F.getDataLayout()), ST(TM->getSubtargetImpl(F)),
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TLI(ST->getTargetLowering()) {}
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TypeSize getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const;
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unsigned getNumberOfRegisters(unsigned ClassID) const;
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unsigned getRegisterClassForType(bool Vector, Type *Ty = nullptr) const;
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unsigned getMaxInterleaveFactor(ElementCount VF);
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const char *getRegisterClassName(unsigned ClassID) const;
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TTI::PopcntSupportKind getPopcntSupport(unsigned TyWidth);
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unsigned getCacheLineSize() const override;
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unsigned getPrefetchDistance() const override;
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bool enableWritePrefetching() const override;
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// TODO: Implement more hooks to provide TTI machinery for LoongArch.
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};
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} // end namespace llvm
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#endif // LLVM_LIB_TARGET_LOONGARCH_LOONGARCHTARGETTRANSFORMINFO_H
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