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llvm-project/llvm/lib/Target/RISCV
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Michael Maitland 5a4945fa4d
[RISCV][SIFIVE] Fix latencies for vector integer arithmetic long latency (#124855) 
These instructions go through a longer latency pipeline of 8.
2025-01-29 09:42:51 -05:00
..
AsmParser
[RISCV] Add MIPS extensions (#121394)
2025-01-28 08:04:09 +01:00
Disassembler
[RISCV] Add MIPS extensions (#121394)
2025-01-28 08:04:09 +01:00
GISel
[RISCV] GISel custom lowering for G_ADD/G_SUB (#121587)
2025-01-07 18:53:10 -08:00
MCA
…
MCTargetDesc
[RISCV] Add MIPS extensions (#121394)
2025-01-28 08:04:09 +01:00
TargetInfo
…
CMakeLists.txt
[RISCV][llvm-exegesis] Add default Pfm cycle counter. (#121866)
2025-01-07 09:51:34 -08:00
RISCV.h
[RISCV] Add MIPS extensions (#121394)
2025-01-28 08:04:09 +01:00
RISCV.td
[RISCV] Add P550 scheduler model. (#124639)
2025-01-27 22:40:05 -08:00
RISCVAsmPrinter.cpp
[XRay][RISCV] RISCV support for XRay (#117368)
2024-12-10 17:57:04 -08:00
RISCVCallingConv.cpp
[RISCV] Add 32 bit GPR sub-register for Zfinx. (#108336)
2024-10-01 22:09:27 -07:00
RISCVCallingConv.h
[RISCV] Reduce the interface to RISCVCCAssignFn. NFC (#107503)
2024-09-06 09:28:33 -07:00
RISCVCallingConv.td
…
RISCVCodeGenPrepare.cpp
[RISCV] Remove unused includes (NFC) (#115814)
2024-11-11 22:54:54 -08:00
RISCVCombine.td
[GISel] Combine (neg (min/max x, (neg x))) into (max/min x, (neg x)) (#120998)
2025-01-02 16:29:34 -08:00
RISCVConstantPoolValue.cpp
[RISCV] Remove unused includes (NFC) (#115814)
2024-11-11 22:54:54 -08:00
RISCVConstantPoolValue.h
[RISCV] Support the large code model. (#70308)
2024-09-09 09:15:07 +08:00
RISCVDeadRegisterDefinitions.cpp
[CodeGen][NewPM] Port LiveStacks analysis to NPM (#118778)
2024-12-06 15:16:07 +05:30
RISCVExpandAtomicPseudoInsts.cpp
…
RISCVExpandPseudoInsts.cpp
[RISCV] Support multiple memory operands in expandRV32ZdinxStore.
2025-01-27 22:10:51 -08:00
RISCVFeatures.td
[RISCV] Add MIPS extensions (#121394)
2025-01-28 08:04:09 +01:00
RISCVFrameLowering.cpp
[RISC-V] Fix incorrect epilogue_begin setting in debug line table (#120623)
2025-01-28 21:03:12 +05:30
RISCVFrameLowering.h
[RISCV] Stack clash protection for dynamic alloca (#122508)
2025-01-16 11:58:42 -08:00
RISCVGatherScatterLowering.cpp
[RISCV] Allow non-loop invariant steps in RISCVGatherScatterLowering (#122244)
2025-01-17 08:58:56 +08:00
RISCVGISel.td
[RISCV] Move GIComplexOperandMatcher and GICustomOperandRenderer next to their SelectionDAG equivalents. NFC (#119729)
2024-12-12 14:41:57 -08:00
RISCVIndirectBranchTracking.cpp
[RISCV] Remove unused includes (NFC) (#115814)
2024-11-11 22:54:54 -08:00
RISCVInsertReadWriteCSR.cpp
…
RISCVInsertVSETVLI.cpp
[RISCV] Use llvm::reverse instead of make_range(rbegin, rend). NFC
2025-01-28 16:08:29 +08:00
RISCVInsertWriteVXRM.cpp
[RISCV] Allow hoisting VXRM writes out of loops speculatively (#110044)
2024-11-27 13:31:39 -08:00
RISCVInstrFormats.td
[RISCV][MC] Support Assembling 48- and 64-bit Instructions (#110022)
2024-10-08 14:09:07 +01:00
RISCVInstrFormatsC.td
[RISCV] Add a default assignment of Inst{12-7} to RVInst16CSS. NFC
2025-01-10 14:28:54 -08:00
RISCVInstrFormatsV.td
…
RISCVInstrGISel.td
[RISCV][GISel] Custom promote s32 G_SHL/ASHR/LSHR on RV64. (#115559)
2024-11-11 20:59:21 -08:00
RISCVInstrInfo.cpp
[RISC-V] Fix incorrect epilogue_begin setting in debug line table (#120623)
2025-01-28 21:03:12 +05:30
RISCVInstrInfo.h
[llvm] Pass MachineInstr flags to storeRegToStackSlot/loadRegFromStackSlot (NFC) (#120622)
2025-01-22 13:36:39 +05:30
RISCVInstrInfo.td
[RISCV] Add MIPS extensions (#121394)
2025-01-28 08:04:09 +01:00
RISCVInstrInfoA.td
[RISCV] Remove unnecessary patterns from RISCVInstrInfoA.td. NFC
2024-12-17 10:24:50 -08:00
RISCVInstrInfoC.td
[RISCV] Add a default assignment of Inst{12-7} to RVInst16CSS. NFC
2025-01-10 14:28:54 -08:00
RISCVInstrInfoD.td
[RISCV][GISel] Support G_MERGE_VALUES/G_UNMERGE_VALUES with Zfa. (#120379)
2025-01-07 07:50:50 -08:00
RISCVInstrInfoF.td
[RISCV][GISel] Add register class to some isel output patterns so they can be imported.
2024-11-24 19:29:52 -08:00
RISCVInstrInfoM.td
…
RISCVInstrInfoSFB.td
[RISCV] Add OperandType for condition code arguments used by select and SFB pseudos. (#114163)
2024-10-29 21:23:31 -07:00
RISCVInstrInfoV.td
[RISCV][MC] Create an AsmOperand for carry-in vmask (#124317)
2025-01-24 13:02:33 -08:00
RISCVInstrInfoVPseudos.td
[RISCV] Mark RVV stores and segmented loads as masked pseudo (#123106)
2025-01-21 09:37:22 -08:00
RISCVInstrInfoVSDPatterns.td
[RISCV] Use _B* suffix for vector mask logic pseudo instructions. (#119787)
2024-12-12 21:11:01 -08:00
RISCVInstrInfoVVLPatterns.td
[RISCV] Use _B* suffix for vector mask logic pseudo instructions. (#119787)
2024-12-12 21:11:01 -08:00
RISCVInstrInfoXCV.td
[RISCV] Fix typo in CV_SH_rr_inc pattern (#120246)
2024-12-17 12:20:17 -08:00
RISCVInstrInfoXMips.td
[RISCV] Add MIPS extensions (#121394)
2025-01-28 08:04:09 +01:00
RISCVInstrInfoXqci.td
[RISCV] Renaming muladdi to muliadd as per v0.5 spec. (#124237)
2025-01-27 20:40:45 -08:00
RISCVInstrInfoXSf.td
[RISCV] Add @earlyclobber to SiFive custom matrix multiply instruction. (#124060)
2025-01-23 08:26:39 -08:00
RISCVInstrInfoXTHead.td
[RISCV] Swap rs1 and rs2 names in TH_ADDSL patterns. NFC
2024-12-29 12:44:33 -08:00
RISCVInstrInfoXVentana.td
…
RISCVInstrInfoXwch.td
[RISCV][NFCI] Rationalize Immediate Definitions (#120718)
2024-12-21 09:47:07 +00:00
RISCVInstrInfoZa.td
…
RISCVInstrInfoZalasr.td
[RISCV][ISEL] Lowering to load-acquire/store-release for RISCV Zalasr (#82914)
2024-12-17 00:19:45 -08:00
RISCVInstrInfoZb.td
[RISCV] Select and/or/xor with certain constants to Zbb ANDN/ORN/XNOR (#120221)
2024-12-19 21:38:20 +01:00
RISCVInstrInfoZc.td
[RISCV] Simplify some RISCVInstrInfoC classes by removing arguments that never change. NFC
2025-01-09 16:21:55 -08:00
RISCVInstrInfoZcmop.td
…
RISCVInstrInfoZfa.td
[RISCV] f32 roundeven pattern missed for Zfa (#118672)
2024-12-04 13:52:20 -08:00
RISCVInstrInfoZfbfmin.td
…
RISCVInstrInfoZfh.td
[RISCV][GISel] Add register class to some isel output patterns so they can be imported.
2024-11-24 19:29:52 -08:00
RISCVInstrInfoZicbo.td
…
RISCVInstrInfoZicfiss.td
…
RISCVInstrInfoZicond.td
…
RISCVInstrInfoZimop.td
…
RISCVInstrInfoZk.td
[RISCV] Combine RVBUnary and RVKUnary into classes that are more similar to ALU(W)_r(r/i). NFC (#111279)
2024-10-06 11:47:30 -07:00
RISCVInstrInfoZvfbf.td
[RISCV] Model dest EEW and fix peepholes not checking EEW (#105945)
2024-09-05 15:27:48 +08:00
RISCVInstrInfoZvk.td
[RISCV] Select Zvkb VANDN for shorter constant loading sequences (#123345)
2025-01-22 07:42:27 +01:00
RISCVISelDAGToDAG.cpp
[RISCV] Select Zvkb VANDN for shorter constant loading sequences (#123345)
2025-01-22 07:42:27 +01:00
RISCVISelDAGToDAG.h
[RISCV] Pattern-match frameindex (#120917)
2024-12-23 13:19:00 +03:00
RISCVISelLowering.cpp
[RISCV] Add MIPS extensions (#121394)
2025-01-28 08:04:09 +01:00
RISCVISelLowering.h
[IA] Generalize the support for power-of-two (de)interleave intrinsics (#123863)
2025-01-23 15:27:51 -08:00
RISCVLandingPadSetup.cpp
[RISCV] Remove unused includes (NFC) (#115814)
2024-11-11 22:54:54 -08:00
RISCVMachineFunctionInfo.cpp
[RISCV] Add stack clash protection (#117612)
2024-12-10 16:48:26 +00:00
RISCVMachineFunctionInfo.h
[RISCV] Stack clash protection for dynamic alloca (#122508)
2025-01-16 11:58:42 -08:00
RISCVMacroFusion.td
…
RISCVMakeCompressible.cpp
[RISCV] Add 32 bit GPR sub-register for Zfinx. (#108336)
2024-10-01 22:09:27 -07:00
RISCVMergeBaseOffset.cpp
[RISCV] Add 32 bit GPR sub-register for Zfinx. (#108336)
2024-10-01 22:09:27 -07:00
RISCVMoveMerger.cpp
…
RISCVOptWInstrs.cpp
…
RISCVPfmCounters.td
[RISCV][llvm-exegesis] Add default Pfm cycle counter. (#121866)
2025-01-07 09:51:34 -08:00
RISCVPostRAExpandPseudoInsts.cpp
[RISCV] Correct the pass name for RISCVPostRAExpandPseudo.
2024-12-05 16:43:30 -08:00
RISCVProcessors.td
[RISCV] Add MIPS extensions (#121394)
2025-01-28 08:04:09 +01:00
RISCVProfiles.td
[RISCV] Use the 'B' extension in RISC-V profile definitions (#113942)
2024-11-10 07:18:05 +00:00
RISCVPushPopOptimizer.cpp
…
RISCVRedundantCopyElimination.cpp
…
RISCVRegisterInfo.cpp
[RISCV] Add register allocation hints for lui/auipc+addi fusion. (#123860)
2025-01-27 11:16:22 -08:00
RISCVRegisterInfo.h
[RISCV] Correct the precedence in isVRegClass (#116579)
2024-11-18 18:12:57 +08:00
RISCVRegisterInfo.td
[RISCV] Merge GPRPair and GPRF64Pair (#116094)
2024-11-20 10:08:55 +00:00
RISCVSchedMIPSP8700.td
[RISCV] Remove duplicate WriteRes<WriteJalr for MIPSP8700. (#123865)
2025-01-22 10:37:01 -08:00
RISCVSchedRocket.td
[RISCV] Use inheritance to simplify usage of the UnsupportedSched* multiclasses. NFC (#120329)
2024-12-17 21:32:50 -08:00
RISCVSchedSiFive7.td
[RISCV][SIFIVE] Fix latencies for vector integer arithmetic long latency (#124855)
2025-01-29 09:42:51 -05:00
RISCVSchedSiFiveP400.td
[RISCV] Update the latencies of MUL and CPOP in SiFive P400 scheduling model (#122007)
2025-01-07 15:01:05 -08:00
RISCVSchedSiFiveP500.td
[RISCV] Add P550 scheduler model. (#124639)
2025-01-27 22:40:05 -08:00
RISCVSchedSiFiveP600.td
[RISCV] Fix the worst case for VSHA2MS in SiFive P400/P600 scheduling models (#116893)
2024-11-21 10:59:46 -08:00
RISCVSchedSyntacoreSCR1.td
[RISCV] Remove some unnecessary UnsupportedSched* that are implied by others. NFC
2025-01-21 18:00:52 -08:00
RISCVSchedSyntacoreSCR7.td
[RISCV] Use inheritance to simplify usage of the UnsupportedSched* multiclasses. NFC (#120329)
2024-12-17 21:32:50 -08:00
RISCVSchedSyntacoreSCR345.td
[RISCV] Use inheritance to simplify usage of the UnsupportedSched* multiclasses. NFC (#120329)
2024-12-17 21:32:50 -08:00
RISCVSchedTTAscalonD8.td
[RISC-V] Base scheduling model for tt-ascalon-d8 (#120160)
2024-12-20 15:30:17 -05:00
RISCVSchedule.td
[RISCV] Add missing ReadFMA16Addend in UnsupportedSchedZfh
2024-12-31 17:22:08 +08:00
RISCVScheduleV.td
[RISCV] Assign different scheduling classes for VMADC/VMSBC (#113009)
2024-10-28 09:37:54 -07:00
RISCVScheduleXSf.td
…
RISCVScheduleZb.td
…
RISCVScheduleZvk.td
[RISCV] Assign separate PseudoVSHA2MS_VV opcodes for each SEW (#114317)
2024-10-31 10:21:14 -07:00
RISCVSchedXiangShanNanHu.td
[RISCV] Use inheritance to simplify usage of the UnsupportedSched* multiclasses. NFC (#120329)
2024-12-17 21:32:50 -08:00
RISCVSelectionDAGInfo.cpp
[SelectionDAG] Virtualize isTargetStrictFPOpcode / isTargetMemoryOpcode (#119969)
2024-12-21 05:29:51 +03:00
RISCVSelectionDAGInfo.h
[SelectionDAG] Virtualize isTargetStrictFPOpcode / isTargetMemoryOpcode (#119969)
2024-12-21 05:29:51 +03:00
RISCVSubtarget.cpp
[RISCV] Add MIPS extensions (#121394)
2025-01-28 08:04:09 +01:00
RISCVSubtarget.h
[RISCV] Add MIPS extensions (#121394)
2025-01-28 08:04:09 +01:00
RISCVSystemOperands.td
[RISCV] Add Enum for CSR encodings. (#121674)
2025-01-06 10:11:29 -08:00
RISCVTargetMachine.cpp
[RISCV] Add MIPS extensions (#121394)
2025-01-28 08:04:09 +01:00
RISCVTargetMachine.h
[SelectionDAG] Add empty implementation of SelectionDAGInfo to some targets (#119968)
2024-12-16 15:13:46 +03:00
RISCVTargetObjectFile.cpp
[RISCV] Support the large code model. (#70308)
2024-09-09 09:15:07 +08:00
RISCVTargetObjectFile.h
…
RISCVTargetTransformInfo.cpp
[RISCV][TTI]Use processShuffleMasks for cost estimations/actual per-register shuffles
2025-01-29 07:18:55 -05:00
RISCVTargetTransformInfo.h
[RISCV] Implement RISCVTTIImpl::getPreferredAddressingMode for HasVendorXCVmem (#120533)
2024-12-31 10:56:28 +08:00
RISCVVectorMaskDAGMutation.cpp
[RISCV] Set a barrier between mask producer and user of V0 (#114012)
2024-11-29 13:25:53 +08:00
RISCVVectorPeephole.cpp
[RISCV] Fix masked->unmasked peephole handling masked pseudos with no passthru (#122253)
2025-01-09 19:54:37 +08:00
RISCVVLOptimizer.cpp
[RISCV][VLOPT] Compute demanded VLs up front (#124530)
2025-01-29 12:39:38 +08:00
RISCVZacasABIFix.cpp
[RISCV] Remove unused includes (NFC) (#115814)
2024-11-11 22:54:54 -08:00