Craig Topper 17f3e00911 Recommit "[GISel][AArch64][AMDGPU][RISCV] Canonicalize (sub X, C) -> (add X, -C) (#114309)"
The increase in fallbacks that was previously reported were not caused
by this change.

Original description:

This matches InstCombine and DAGCombine.

RISC-V only has an ADDI instruction so without this we need additional
patterns to do the conversion.

Some of the AMDGPU tests look like possible regressions. Maybe some
patterns from isel aren't imported.
2024-11-08 10:21:46 -08:00

370 lines
9.7 KiB
YAML

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple aarch64 -run-pass=aarch64-prelegalizer-combiner %s -o - | FileCheck %s
---
name: ZeroMinusAPlusB
body: |
bb.0:
liveins: $w0, $w1
; CHECK-LABEL: name: ZeroMinusAPlusB
; CHECK: liveins: $w0, $w1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %a:_(s32) = COPY $w0
; CHECK-NEXT: %b:_(s32) = COPY $w0
; CHECK-NEXT: %add:_(s32) = G_SUB %b, %a
; CHECK-NEXT: $w0 = COPY %add(s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%x:_(s32) = COPY $w0
%a:_(s32) = COPY $w0
%b:_(s32) = COPY $w0
%zero:_(s32) = G_CONSTANT i32 0
%sub:_(s32) = G_SUB %zero, %a
%add:_(s32) = G_ADD %sub, %b
$w0 = COPY %add
RET_ReallyLR implicit $w0
...
---
name: ZeroMinusAPlusB_multi_use
body: |
bb.0:
liveins: $w0, $w1
; CHECK-LABEL: name: ZeroMinusAPlusB_multi_use
; CHECK: liveins: $w0, $w1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %a:_(s32) = COPY $w0
; CHECK-NEXT: %b:_(s32) = COPY $w0
; CHECK-NEXT: %zero:_(s32) = G_CONSTANT i32 0
; CHECK-NEXT: %sub:_(s32) = G_SUB %zero, %a
; CHECK-NEXT: %add:_(s32) = G_SUB %b, %a
; CHECK-NEXT: $w0 = COPY %add(s32)
; CHECK-NEXT: $w0 = COPY %sub(s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%x:_(s32) = COPY $w0
%a:_(s32) = COPY $w0
%b:_(s32) = COPY $w0
%zero:_(s32) = G_CONSTANT i32 0
%sub:_(s32) = G_SUB %zero, %a
%add:_(s32) = G_ADD %sub, %b
$w0 = COPY %add
$w0 = COPY %sub
RET_ReallyLR implicit $w0
...
---
name: APlusZeroMiunusB
body: |
bb.0:
liveins: $w0, $w1
; CHECK-LABEL: name: APlusZeroMiunusB
; CHECK: liveins: $w0, $w1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %a:_(s64) = COPY $x1
; CHECK-NEXT: %b:_(s64) = COPY $x2
; CHECK-NEXT: %add:_(s64) = G_SUB %a, %b
; CHECK-NEXT: $x0 = COPY %add(s64)
; CHECK-NEXT: RET_ReallyLR implicit $x0
%x:_(s64) = COPY $x0
%a:_(s64) = COPY $x1
%b:_(s64) = COPY $x2
%zero:_(s64) = G_CONSTANT i64 0
%sub:_(s64) = G_SUB %zero, %b
%add:_(s64) = G_ADD %a, %sub
$x0 = COPY %add
RET_ReallyLR implicit $x0
...
---
name: APlusBMinusB
body: |
bb.0:
liveins: $w0, $w1
; CHECK-LABEL: name: APlusBMinusB
; CHECK: liveins: $w0, $w1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %b:_(s64) = COPY $x1
; CHECK-NEXT: $x0 = COPY %b(s64)
; CHECK-NEXT: RET_ReallyLR implicit $x0
%a:_(s64) = COPY $x0
%b:_(s64) = COPY $x1
%zero:_(s64) = G_CONSTANT i64 0
%sub:_(s64) = G_SUB %b, %a
%add:_(s64) = G_ADD %a, %sub
$x0 = COPY %add
RET_ReallyLR implicit $x0
...
---
name: BMinusAPlusA
body: |
bb.0:
liveins: $w0, $w1
; CHECK-LABEL: name: BMinusAPlusA
; CHECK: liveins: $w0, $w1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %b:_(s64) = COPY $x1
; CHECK-NEXT: $x0 = COPY %b(s64)
; CHECK-NEXT: RET_ReallyLR implicit $x0
%a:_(s64) = COPY $x0
%b:_(s64) = COPY $x1
%zero:_(s64) = G_CONSTANT i64 0
%sub:_(s64) = G_SUB %b, %a
%add:_(s64) = G_ADD %sub, %a
$x0 = COPY %add
RET_ReallyLR implicit $x0
...
---
name: AMinusBPlusCMinusA
body: |
bb.0:
liveins: $w0, $w1
; CHECK-LABEL: name: AMinusBPlusCMinusA
; CHECK: liveins: $w0, $w1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %b:_(s64) = COPY $x1
; CHECK-NEXT: %c:_(s64) = COPY $x2
; CHECK-NEXT: %add:_(s64) = G_SUB %c, %b
; CHECK-NEXT: $x0 = COPY %add(s64)
; CHECK-NEXT: RET_ReallyLR implicit $x0
%a:_(s64) = COPY $x0
%b:_(s64) = COPY $x1
%c:_(s64) = COPY $x2
%zero:_(s64) = G_CONSTANT i64 0
%sub2:_(s64) = G_SUB %c, %a
%sub1:_(s64) = G_SUB %a, %b
%add:_(s64) = G_ADD %sub1, %sub2
$x0 = COPY %add
RET_ReallyLR implicit $x0
...
---
name: AMinusBPlusBMinusC
body: |
bb.0:
liveins: $w0, $w1
; CHECK-LABEL: name: AMinusBPlusBMinusC
; CHECK: liveins: $w0, $w1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %a:_(s64) = COPY $x0
; CHECK-NEXT: %c:_(s64) = COPY $x2
; CHECK-NEXT: %add:_(s64) = G_SUB %a, %c
; CHECK-NEXT: $x0 = COPY %add(s64)
; CHECK-NEXT: RET_ReallyLR implicit $x0
%a:_(s64) = COPY $x0
%b:_(s64) = COPY $x1
%c:_(s64) = COPY $x2
%zero:_(s64) = G_CONSTANT i64 0
%sub2:_(s64) = G_SUB %b, %c
%sub1:_(s64) = G_SUB %a, %b
%add:_(s64) = G_ADD %sub1, %sub2
$x0 = COPY %add
RET_ReallyLR implicit $x0
...
---
name: APlusBMinusAplusC
body: |
bb.0:
liveins: $w0, $w1
; CHECK-LABEL: name: APlusBMinusAplusC
; CHECK: liveins: $w0, $w1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %b:_(s64) = COPY $x1
; CHECK-NEXT: %c:_(s64) = COPY $x2
; CHECK-NEXT: %add:_(s64) = G_SUB %b, %c
; CHECK-NEXT: $x0 = COPY %add(s64)
; CHECK-NEXT: RET_ReallyLR implicit $x0
%a:_(s64) = COPY $x0
%b:_(s64) = COPY $x1
%c:_(s64) = COPY $x2
%zero:_(s64) = G_CONSTANT i64 0
%add1:_(s64) = G_ADD %a, %c
%sub1:_(s64) = G_SUB %b, %add1
%add:_(s64) = G_ADD %a, %sub1
$x0 = COPY %add
RET_ReallyLR implicit $x0
...
---
name: APlusBMinusCPlusA
body: |
bb.0:
liveins: $w0, $w1
; CHECK-LABEL: name: APlusBMinusCPlusA
; CHECK: liveins: $w0, $w1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %b:_(s64) = COPY $x1
; CHECK-NEXT: %c:_(s64) = COPY $x2
; CHECK-NEXT: %add:_(s64) = G_SUB %b, %c
; CHECK-NEXT: $x0 = COPY %add(s64)
; CHECK-NEXT: RET_ReallyLR implicit $x0
%a:_(s64) = COPY $x0
%b:_(s64) = COPY $x1
%c:_(s64) = COPY $x2
%zero:_(s64) = G_CONSTANT i64 0
%add1:_(s64) = G_ADD %c, %a
%sub1:_(s64) = G_SUB %b, %add1
%add:_(s64) = G_ADD %a, %sub1
$x0 = COPY %add
RET_ReallyLR implicit $x0
...
---
name: APlusBMinusCPlusA_BV
body: |
bb.0:
liveins: $w0, $w1
; CHECK-LABEL: name: APlusBMinusCPlusA_BV
; CHECK: liveins: $w0, $w1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %a1:_(s64) = COPY $x0
; CHECK-NEXT: %b1:_(s64) = COPY $x1
; CHECK-NEXT: %c1:_(s64) = COPY $x2
; CHECK-NEXT: %b:_(<2 x s64>) = G_BUILD_VECTOR %b1(s64), %ba:_(s64)
; CHECK-NEXT: %c:_(<2 x s64>) = G_BUILD_VECTOR %a1(s64), %c1(s64)
; CHECK-NEXT: %add:_(<2 x s64>) = G_SUB %b, %c
; CHECK-NEXT: $q0 = COPY %add(<2 x s64>)
; CHECK-NEXT: RET_ReallyLR implicit $x0
%a1:_(s64) = COPY $x0
%b1:_(s64) = COPY $x1
%c1:_(s64) = COPY $x2
%a:_(<2 x s64>) = G_BUILD_VECTOR %a1:_(s64), %b1:_(s64)
%b:_(<2 x s64>) = G_BUILD_VECTOR %b1:_(s64), %ba:_(s64)
%c:_(<2 x s64>) = G_BUILD_VECTOR %a1:_(s64), %c1:_(s64)
%zero:_(s64) = G_CONSTANT i64 0
%add1:_(<2 x s64>) = G_ADD %c, %a
%sub1:_(<2 x s64>) = G_SUB %b, %add1
%add:_(<2 x s64>) = G_ADD %a, %sub1
$q0 = COPY %add
RET_ReallyLR implicit $x0
...
---
name: APlusC1MinusC2
body: |
bb.0:
liveins: $w0, $w1
; CHECK-LABEL: name: APlusC1MinusC2
; CHECK: liveins: $w0, $w1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %a:_(s64) = COPY $x0
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -2
; CHECK-NEXT: %sub:_(s64) = G_ADD %a, [[C]]
; CHECK-NEXT: $x0 = COPY %sub(s64)
; CHECK-NEXT: RET_ReallyLR implicit $x0
%a:_(s64) = COPY $x0
%c1:_(s64) = G_CONSTANT i64 5
%c2:_(s64) = G_CONSTANT i64 7
%add:_(s64) = G_ADD %a, %c1
%sub:_(s64) = G_SUB %add, %c2
$x0 = COPY %sub
RET_ReallyLR implicit $x0
...
---
name: C2MinusAPlusC1
body: |
bb.0:
liveins: $w0, $w1
; CHECK-LABEL: name: C2MinusAPlusC1
; CHECK: liveins: $w0, $w1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %a:_(s64) = COPY $x0
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 5
; CHECK-NEXT: %sub:_(s64) = G_SUB [[C]], %a
; CHECK-NEXT: $x0 = COPY %sub(s64)
; CHECK-NEXT: RET_ReallyLR implicit $x0
%a:_(s64) = COPY $x0
%c1:_(s64) = G_CONSTANT i64 4
%c2:_(s64) = G_CONSTANT i64 9
%add:_(s64) = G_ADD %a, %c1
%sub:_(s64) = G_SUB %c2, %add
$x0 = COPY %sub
RET_ReallyLR implicit $x0
...
---
name: AMinusC1MinusC2
body: |
bb.0:
liveins: $w0, $w1
; CHECK-LABEL: name: AMinusC1MinusC2
; CHECK: liveins: $w0, $w1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %a:_(s64) = COPY $x0
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -71
; CHECK-NEXT: %sub:_(s64) = G_ADD %a, [[C]]
; CHECK-NEXT: $x0 = COPY %sub(s64)
; CHECK-NEXT: RET_ReallyLR implicit $x0
%a:_(s64) = COPY $x0
%c1:_(s64) = G_CONSTANT i64 11
%c2:_(s64) = G_CONSTANT i64 60
%sub1:_(s64) = G_SUB %a, %c1
%sub:_(s64) = G_SUB %sub1, %c2
$x0 = COPY %sub
RET_ReallyLR implicit $x0
...
---
name: C1Minus2MinusC2
body: |
bb.0:
liveins: $w0, $w1
; CHECK-LABEL: name: C1Minus2MinusC2
; CHECK: liveins: $w0, $w1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %a:_(s64) = COPY $x0
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -49
; CHECK-NEXT: %sub:_(s64) = G_SUB [[C]], %a
; CHECK-NEXT: $x0 = COPY %sub(s64)
; CHECK-NEXT: RET_ReallyLR implicit $x0
%a:_(s64) = COPY $x0
%c1:_(s64) = G_CONSTANT i64 11
%c2:_(s64) = G_CONSTANT i64 60
%sub1:_(s64) = G_SUB %c1, %a
%sub:_(s64) = G_SUB %sub1, %c2
$x0 = COPY %sub
RET_ReallyLR implicit $x0
...
---
name: AMinusC2PlusC2
body: |
bb.0:
liveins: $w0, $w1
; CHECK-LABEL: name: AMinusC2PlusC2
; CHECK: liveins: $w0, $w1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %a:_(s64) = COPY $x0
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 43
; CHECK-NEXT: %add:_(s64) = G_ADD %a, [[C]]
; CHECK-NEXT: $x0 = COPY %add(s64)
; CHECK-NEXT: RET_ReallyLR implicit $x0
%a:_(s64) = COPY $x0
%c1:_(s64) = G_CONSTANT i64 13
%c2:_(s64) = G_CONSTANT i64 56
%sub:_(s64) = G_SUB %a, %c1
%add:_(s64) = G_ADD %sub, %c2
$x0 = COPY %add
RET_ReallyLR implicit $x0