2208c97c1b
Similar to 806761a7629df268c8aed49657aeccffa6bca449 -mtriple= specifies the full target triple while -march= merely sets the architecture part of the default target triple, leaving a target triple which may not make sense. Therefore, -march= is error-prone and not recommended for tests without a target triple. The issue has been benign as we recognize $unknown-apple-darwin as ELF instead of rejecting it outrightly.
308 lines
8.7 KiB
LLVM
308 lines
8.7 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=hexagon < %s | FileCheck %s
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define <64 x i8> @test0000(<64 x i8> %a0, i8 %a1) #0 {
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; CHECK-LABEL: test0000:
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; CHECK: // %bb.0:
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; CHECK-NEXT: {
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; CHECK-NEXT: v1:0.uh = vzxt(v0.ub)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: v0.h = vasl(v0.h,r0)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: v1.h = vasl(v1.h,r0)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: v0.b = vshuffe(v1.b,v0.b)
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; CHECK-NEXT: jumpr r31
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; CHECK-NEXT: }
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%b0 = insertelement <64 x i8> zeroinitializer, i8 %a1, i32 0
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%b1 = shufflevector <64 x i8> %b0, <64 x i8> undef, <64 x i32> zeroinitializer
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%v0 = shl <64 x i8> %a0, %b1
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ret <64 x i8> %v0
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}
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define <64 x i8> @test0001(<64 x i8> %a0, i8 %a1) #0 {
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; CHECK-LABEL: test0001:
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; CHECK: // %bb.0:
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; CHECK-NEXT: {
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; CHECK-NEXT: v1:0.h = vsxt(v0.b)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: v0.h = vasr(v0.h,r0)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: v1.h = vasr(v1.h,r0)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: v0.b = vshuffe(v1.b,v0.b)
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; CHECK-NEXT: jumpr r31
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; CHECK-NEXT: }
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%b0 = insertelement <64 x i8> zeroinitializer, i8 %a1, i32 0
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%b1 = shufflevector <64 x i8> %b0, <64 x i8> undef, <64 x i32> zeroinitializer
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%v0 = ashr <64 x i8> %a0, %b1
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ret <64 x i8> %v0
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}
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define <64 x i8> @test0002(<64 x i8> %a0, i8 %a1) #0 {
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; CHECK-LABEL: test0002:
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; CHECK: // %bb.0:
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; CHECK-NEXT: {
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; CHECK-NEXT: v1:0.uh = vzxt(v0.ub)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: v0.uh = vlsr(v0.uh,r0)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: v1.uh = vlsr(v1.uh,r0)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: v0.b = vshuffe(v1.b,v0.b)
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; CHECK-NEXT: jumpr r31
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; CHECK-NEXT: }
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%b0 = insertelement <64 x i8> zeroinitializer, i8 %a1, i32 0
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%b1 = shufflevector <64 x i8> %b0, <64 x i8> undef, <64 x i32> zeroinitializer
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%v0 = lshr <64 x i8> %a0, %b1
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ret <64 x i8> %v0
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}
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define <32 x i16> @test0010(<32 x i16> %a0, i16 %a1) #0 {
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; CHECK-LABEL: test0010:
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; CHECK: // %bb.0:
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; CHECK-NEXT: {
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; CHECK-NEXT: v0.h = vasl(v0.h,r0)
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; CHECK-NEXT: jumpr r31
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; CHECK-NEXT: }
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%b0 = insertelement <32 x i16> zeroinitializer, i16 %a1, i32 0
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%b1 = shufflevector <32 x i16> %b0, <32 x i16> undef, <32 x i32> zeroinitializer
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%v0 = shl <32 x i16> %a0, %b1
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ret <32 x i16> %v0
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}
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define <32 x i16> @test0011(<32 x i16> %a0, i16 %a1) #0 {
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; CHECK-LABEL: test0011:
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; CHECK: // %bb.0:
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; CHECK-NEXT: {
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; CHECK-NEXT: v0.h = vasr(v0.h,r0)
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; CHECK-NEXT: jumpr r31
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; CHECK-NEXT: }
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%b0 = insertelement <32 x i16> zeroinitializer, i16 %a1, i32 0
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%b1 = shufflevector <32 x i16> %b0, <32 x i16> undef, <32 x i32> zeroinitializer
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%v0 = ashr <32 x i16> %a0, %b1
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ret <32 x i16> %v0
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}
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define <32 x i16> @test0012(<32 x i16> %a0, i16 %a1) #0 {
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; CHECK-LABEL: test0012:
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; CHECK: // %bb.0:
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; CHECK-NEXT: {
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; CHECK-NEXT: v0.uh = vlsr(v0.uh,r0)
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; CHECK-NEXT: jumpr r31
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; CHECK-NEXT: }
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%b0 = insertelement <32 x i16> zeroinitializer, i16 %a1, i32 0
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%b1 = shufflevector <32 x i16> %b0, <32 x i16> undef, <32 x i32> zeroinitializer
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%v0 = lshr <32 x i16> %a0, %b1
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ret <32 x i16> %v0
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}
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define <16 x i32> @test0020(<16 x i32> %a0, i32 %a1) #0 {
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; CHECK-LABEL: test0020:
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; CHECK: // %bb.0:
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; CHECK-NEXT: {
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; CHECK-NEXT: v0.w = vasl(v0.w,r0)
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; CHECK-NEXT: jumpr r31
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; CHECK-NEXT: }
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%b0 = insertelement <16 x i32> zeroinitializer, i32 %a1, i32 0
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%b1 = shufflevector <16 x i32> %b0, <16 x i32> undef, <16 x i32> zeroinitializer
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%v0 = shl <16 x i32> %a0, %b1
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ret <16 x i32> %v0
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}
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define <16 x i32> @test0021(<16 x i32> %a0, i32 %a1) #0 {
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; CHECK-LABEL: test0021:
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; CHECK: // %bb.0:
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; CHECK-NEXT: {
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; CHECK-NEXT: v0.w = vasr(v0.w,r0)
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; CHECK-NEXT: jumpr r31
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; CHECK-NEXT: }
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%b0 = insertelement <16 x i32> zeroinitializer, i32 %a1, i32 0
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%b1 = shufflevector <16 x i32> %b0, <16 x i32> undef, <16 x i32> zeroinitializer
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%v0 = ashr <16 x i32> %a0, %b1
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ret <16 x i32> %v0
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}
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define <16 x i32> @test0022(<16 x i32> %a0, i32 %a1) #0 {
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; CHECK-LABEL: test0022:
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; CHECK: // %bb.0:
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; CHECK-NEXT: {
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; CHECK-NEXT: v0.uw = vlsr(v0.uw,r0)
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; CHECK-NEXT: jumpr r31
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; CHECK-NEXT: }
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%b0 = insertelement <16 x i32> zeroinitializer, i32 %a1, i32 0
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%b1 = shufflevector <16 x i32> %b0, <16 x i32> undef, <16 x i32> zeroinitializer
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%v0 = lshr <16 x i32> %a0, %b1
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ret <16 x i32> %v0
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}
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define <16 x i32> @test0023(<16 x i32> %a0, <16 x i32> %a1, i32 %a2) #0 {
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; CHECK-LABEL: test0023:
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; CHECK: // %bb.0:
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; CHECK-NEXT: {
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; CHECK-NEXT: v0.w += vasl(v1.w,r0)
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; CHECK-NEXT: jumpr r31
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; CHECK-NEXT: }
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%b0 = insertelement <16 x i32> zeroinitializer, i32 %a2, i32 0
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%b1 = shufflevector <16 x i32> %b0, <16 x i32> undef, <16 x i32> zeroinitializer
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%v0 = shl <16 x i32> %a1, %b1
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%v1 = add <16 x i32> %a0, %v0
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ret <16 x i32> %v1
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}
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define <16 x i32> @test0024(<16 x i32> %a0, <16 x i32> %a1, i32 %a2) #0 {
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; CHECK-LABEL: test0024:
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; CHECK: // %bb.0:
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; CHECK-NEXT: {
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; CHECK-NEXT: v0.w += vasr(v1.w,r0)
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; CHECK-NEXT: jumpr r31
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; CHECK-NEXT: }
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%b0 = insertelement <16 x i32> zeroinitializer, i32 %a2, i32 0
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%b1 = shufflevector <16 x i32> %b0, <16 x i32> undef, <16 x i32> zeroinitializer
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%v0 = ashr <16 x i32> %a1, %b1
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%v1 = add <16 x i32> %a0, %v0
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ret <16 x i32> %v1
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}
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define <64 x i8> @test0030(<64 x i8> %a0, <64 x i8> %a1) #0 {
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; CHECK-LABEL: test0030:
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; CHECK: // %bb.0:
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; CHECK-NEXT: {
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; CHECK-NEXT: v3:2.uh = vzxt(v0.ub)
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; CHECK-NEXT: v31:30.uh = vzxt(v1.ub)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: v0.h = vasl(v2.h,v30.h)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: v1.h = vasl(v3.h,v31.h)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: v0.b = vshuffe(v1.b,v0.b)
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; CHECK-NEXT: jumpr r31
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; CHECK-NEXT: }
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%v0 = shl <64 x i8> %a0, %a1
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ret <64 x i8> %v0
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}
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define <64 x i8> @test0031(<64 x i8> %a0, <64 x i8> %a1) #0 {
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; CHECK-LABEL: test0031:
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; CHECK: // %bb.0:
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; CHECK-NEXT: {
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; CHECK-NEXT: v3:2.h = vsxt(v0.b)
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; CHECK-NEXT: v31:30.uh = vzxt(v1.ub)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: v0.h = vasr(v2.h,v30.h)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: v1.h = vasr(v3.h,v31.h)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: v0.b = vshuffe(v1.b,v0.b)
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; CHECK-NEXT: jumpr r31
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; CHECK-NEXT: }
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%v0 = ashr <64 x i8> %a0, %a1
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ret <64 x i8> %v0
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}
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define <64 x i8> @test0032(<64 x i8> %a0, <64 x i8> %a1) #0 {
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; CHECK-LABEL: test0032:
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; CHECK: // %bb.0:
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; CHECK-NEXT: {
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; CHECK-NEXT: v3:2.uh = vzxt(v0.ub)
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; CHECK-NEXT: v31:30.uh = vzxt(v1.ub)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: v0.h = vlsr(v2.h,v30.h)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: v1.h = vlsr(v3.h,v31.h)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: v0.b = vshuffe(v1.b,v0.b)
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; CHECK-NEXT: jumpr r31
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; CHECK-NEXT: }
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%v0 = lshr <64 x i8> %a0, %a1
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ret <64 x i8> %v0
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}
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define <32 x i16> @test0040(<32 x i16> %a0, <32 x i16> %a1) #0 {
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; CHECK-LABEL: test0040:
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; CHECK: // %bb.0:
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; CHECK-NEXT: {
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; CHECK-NEXT: v0.h = vasl(v0.h,v1.h)
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; CHECK-NEXT: jumpr r31
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; CHECK-NEXT: }
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%v0 = shl <32 x i16> %a0, %a1
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ret <32 x i16> %v0
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}
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define <32 x i16> @test0041(<32 x i16> %a0, <32 x i16> %a1) #0 {
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; CHECK-LABEL: test0041:
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; CHECK: // %bb.0:
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; CHECK-NEXT: {
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; CHECK-NEXT: v0.h = vasr(v0.h,v1.h)
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; CHECK-NEXT: jumpr r31
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; CHECK-NEXT: }
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%v0 = ashr <32 x i16> %a0, %a1
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ret <32 x i16> %v0
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}
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define <32 x i16> @test0042(<32 x i16> %a0, <32 x i16> %a1) #0 {
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; CHECK-LABEL: test0042:
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; CHECK: // %bb.0:
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; CHECK-NEXT: {
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; CHECK-NEXT: v0.h = vlsr(v0.h,v1.h)
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; CHECK-NEXT: jumpr r31
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; CHECK-NEXT: }
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%v0 = lshr <32 x i16> %a0, %a1
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ret <32 x i16> %v0
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}
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define <16 x i32> @test0050(<16 x i32> %a0, <16 x i32> %a1) #0 {
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; CHECK-LABEL: test0050:
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; CHECK: // %bb.0:
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; CHECK-NEXT: {
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; CHECK-NEXT: v0.w = vasl(v0.w,v1.w)
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; CHECK-NEXT: jumpr r31
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; CHECK-NEXT: }
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%v0 = shl <16 x i32> %a0, %a1
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ret <16 x i32> %v0
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}
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define <16 x i32> @test0051(<16 x i32> %a0, <16 x i32> %a1) #0 {
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; CHECK-LABEL: test0051:
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; CHECK: // %bb.0:
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; CHECK-NEXT: {
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; CHECK-NEXT: v0.w = vasr(v0.w,v1.w)
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; CHECK-NEXT: jumpr r31
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; CHECK-NEXT: }
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%v0 = ashr <16 x i32> %a0, %a1
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ret <16 x i32> %v0
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}
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define <16 x i32> @test0052(<16 x i32> %a0, <16 x i32> %a1) #0 {
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; CHECK-LABEL: test0052:
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; CHECK: // %bb.0:
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; CHECK-NEXT: {
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; CHECK-NEXT: v0.w = vlsr(v0.w,v1.w)
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; CHECK-NEXT: jumpr r31
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; CHECK-NEXT: }
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%v0 = lshr <16 x i32> %a0, %a1
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ret <16 x i32> %v0
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}
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attributes #0 = { nounwind readnone "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length64b" }
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