Craig Topper 88c18da37d

[RISCV] Rename suffixes on VCPOP/VMSBF/VMSET/etc pseudos. NFC (#119785) ...

These are suffixed with B1, B2, B4, B8, B16, B32, or B64 which I think
these were supposed to match the naming of the vbool types from C where
the number should be SEW/LMUL. So the smallest mask is 64 and the
largest is 1. This provides a compact syntax for describing the 7
possible ratios between LMUL and SEW.

We had the instruction names in the opposite order.

2024-12-12 16:17:21 -08:00

..

rvv

[RISCV] Rename suffixes on VCPOP/VMSBF/VMSET/etc pseudos. NFC (#119785)

2024-12-12 16:17:21 -08:00

alu_m-rv32.mir

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alu_m-rv64.mir

[RISCV][GISel] Remove s32 as a legal type for G_SMUL on RV64.

2024-11-11 15:08:50 -08:00

alu-rv32.mir

[RISCV][GISel] Port TrailingOnesMask PatLeaf. (#119427)

2024-12-10 22:17:52 -08:00

alu-rv64.mir

[RISCV][GISel] Custom promote s32 G_SHL/ASHR/LSHR on RV64. (#115559)

2024-11-11 20:59:21 -08:00

brcond-rv32.mir

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brcond-rv64.mir

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brindirect-rv32.mir

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brindirect-rv64.mir

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bswap-rv32.mir

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bswap-rv64.mir

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constant32.mir

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constant64.mir

[RISCV][GISel] Promote s32 G_CONSTANT on RV64.

2024-11-11 23:35:02 -08:00

copy32.mir

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copy64.mir

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ctlz-rv32.mir

[RISCV][GISel] Add missing tests for G_CTLZ/CTTZ instruction selection. NFC

2024-08-09 12:10:34 -07:00

ctlz-rv64.mir

[RISCV][GISel] Remove s32 support for G_CTPOP/CTLZ/CTTZ on RV64. (#115101)

2024-11-07 10:40:14 -08:00

ctpop-rv32.mir

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ctpop-rv64.mir

[RISCV][GISel] Remove s32 support for G_CTPOP/CTLZ/CTTZ on RV64. (#115101)

2024-11-07 10:40:14 -08:00

cttz-rv32.mir

[RISCV][GISel] Add missing tests for G_CTLZ/CTTZ instruction selection. NFC

2024-08-09 12:10:34 -07:00

cttz-rv64.mir

[RISCV][GISel] Remove s32 support for G_CTPOP/CTLZ/CTTZ on RV64. (#115101)

2024-11-07 10:40:14 -08:00

fcmp-f16-rv32.mir

[RISCV][GISel] Support fcmp and fclass for Zfh. (#96696)

2024-06-26 09:53:13 -07:00

fcmp-f16-rv64.mir

[RISCV][GISel] Support fcmp and fclass for Zfh. (#96696)

2024-06-26 09:53:13 -07:00

fcmp-rv32.mir

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fcmp-rv64.mir

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fp-arith-f16.mir

[RISCV][GISel] Add fcopysign tests with mismatched types. NFC (#115364)

2024-11-07 17:07:31 -08:00

fp-arith.mir

[RISCV][GISel] Add fcopysign tests with mismatched types. NFC (#115364)

2024-11-07 17:07:31 -08:00

fp-constant-f16.mir

[RISCV][GISel] Support G_FCONSTANT for Zfh.

2024-06-25 14:10:25 -07:00

fp-constant.mir

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fp-ext-trunc-f16.mir

[RISCV][GISel] Support G_FPEXT/FPTRUNC with ZFh.

2024-06-26 11:11:05 -07:00

fp-ext-trunc.mir

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fp-load-store.mir

[RISCV][GISel] Make loads/stores with s16 register type and s16 memory type legal.

2024-11-17 11:39:59 -08:00

fp-select-rv32.mir

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fp-select-rv64.mir

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fptoi-f16-rv32.mir

[RISCV][GISel] Support fptoi and itofp for Zfh. (#96707)

2024-06-26 09:53:37 -07:00

fptoi-f16-rv64.mir

[RISCV][GISel] Custom promote s32 G_FPTOSI/FPTOUI on RV64. (#115268)

2024-11-07 17:08:58 -08:00

fptoi-rv32.mir

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fptoi-rv64.mir

[RISCV][GISel] Custom promote s32 G_FPTOSI/FPTOUI on RV64. (#115268)

2024-11-07 17:08:58 -08:00

frame-index-rv32.mir

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frame-index-rv64.mir

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global-value32.mir

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global-value64.mir

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icmp-rv32.mir

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icmp-rv64.mir

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implicit-def-rv32.mir

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implicit-def-rv64.mir

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int-ptr-cast-rv32.mir

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int-ptr-cast-rv64.mir

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is-fpclass-f16-rv32.mir

[RISCV][GISel] Support fcmp and fclass for Zfh. (#96696)

2024-06-26 09:53:13 -07:00

is-fpclass-f16-rv64.mir

[RISCV][GISel] Support fcmp and fclass for Zfh. (#96696)

2024-06-26 09:53:13 -07:00

is-fpclass-rv32.mir

[RISCV][GISel] Add missing fclass tests. NFC (#96694)

2024-06-26 09:07:18 -07:00

is-fpclass-rv64.mir

[RISCV][GISel] Add missing fclass tests. NFC (#96694)

2024-06-26 09:07:18 -07:00

itofp-f16-rv32.mir

[RISCV][GISel] Support fptoi and itofp for Zfh. (#96707)

2024-06-26 09:53:37 -07:00

itofp-f16-rv64.mir

[RISCV][GISel] Remove s32 input support for G_SITOFP/UITOFP on RV64. (#115236)

2024-11-07 13:57:11 -08:00

itofp-rv32.mir

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itofp-rv64.mir

[RISCV][GISel] Remove s32 input support for G_SITOFP/UITOFP on RV64. (#115236)

2024-11-07 13:57:11 -08:00

load-rv32.mir

[RISCV][GISel] Make extended loads and truncating stores with s16 register type and s8 memory type legal.

2024-11-19 11:57:35 -08:00

load-rv64.mir

[RISCV][GISel] Make extended loads and truncating stores with s16 register type and s8 memory type legal.

2024-11-19 11:57:35 -08:00

merge-unmerge-rv32.mir

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minmax-rv32.mir

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minmax-rv64.mir

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phi-rv32.mir

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phi-rv64.mir

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ptradd-rv32.mir

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ptradd-rv64.mir

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ptrmask-rv32.mir

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ptrmask-rv64.mir

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rotate-rv32.mir

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rotate-rv64.mir

[RISCV][GISel] Custom promote s32 G_ROTL/ROTR on RV64. (#115107)

2024-11-07 13:24:22 -08:00

select-rv32.mir

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select-rv64.mir

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sext-rv64.mir

[RISCV][GISel] Promote s32 G_CONSTANT on RV64.

2024-11-11 23:35:02 -08:00

shift-rv32.mir

[RISCV][GlobalISel] Fix selectShiftMask when shift mask is created from G_AND (#89602)

2024-05-09 09:18:10 -04:00

shift-rv64.mir

[RISCV][GISel] Promote s32 G_CONSTANT on RV64.

2024-11-11 23:35:02 -08:00

store-rv32.mir

[RISCV][GISel] Make extended loads and truncating stores with s16 register type and s8 memory type legal.

2024-11-19 11:57:35 -08:00

store-rv64.mir

[RISCV][GISel] Make extended loads and truncating stores with s16 register type and s8 memory type legal.

2024-11-19 11:57:35 -08:00

trap.mir

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zba-rv32.mir

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zba-rv64.mir

[RISCV][GISel] Remove most patterns that look for a zext i32->i64 and another integer instruction.

2024-11-14 14:03:02 -08:00

zext-rv64.mir

[RISCV][GISel] Promote s32 G_CONSTANT on RV64.

2024-11-11 23:35:02 -08:00