9122c5235e
This is based on other targets like PPC/AArch64 and some experiments. This PR will only enable bidirectional scheduling and tracking register pressure. Disclaimer: I haven't tested it on many cores, maybe we should make some options being features. I believe downstreams must have tried this before, so feedbacks are welcome.
90 lines
3.3 KiB
LLVM
90 lines
3.3 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK
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declare <vscale x 2 x i64> @llvm.bitreverse.nxv2i64(<vscale x 2 x i64>)
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define i32 @splat_vector_split_i64() {
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; CHECK-LABEL: splat_vector_split_i64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: addi sp, sp, -16
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; CHECK-NEXT: .cfi_def_cfa_offset 16
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; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma
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; CHECK-NEXT: vmv.v.i v10, 3
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; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma
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; CHECK-NEXT: vmv.v.i v8, 0
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; CHECK-NEXT: lui a1, 1044480
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; CHECK-NEXT: li a2, 56
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; CHECK-NEXT: li a3, 40
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; CHECK-NEXT: lui a4, 16
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; CHECK-NEXT: lui a0, 4080
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; CHECK-NEXT: addi a5, sp, 8
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; CHECK-NEXT: sw a1, 8(sp)
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; CHECK-NEXT: sw zero, 12(sp)
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; CHECK-NEXT: addi a1, a4, -256
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; CHECK-NEXT: vsetivli zero, 4, e64, m2, tu, ma
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; CHECK-NEXT: vslideup.vi v8, v10, 3
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; CHECK-NEXT: vsetvli a4, zero, e64, m2, ta, ma
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; CHECK-NEXT: vlse64.v v10, (a5), zero
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; CHECK-NEXT: vsrl.vx v12, v8, a2
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; CHECK-NEXT: vsrl.vx v14, v8, a3
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; CHECK-NEXT: vsrl.vi v16, v8, 24
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; CHECK-NEXT: vsll.vx v18, v8, a2
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; CHECK-NEXT: vand.vx v14, v14, a1
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; CHECK-NEXT: vor.vv v14, v14, v12
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; CHECK-NEXT: vand.vx v12, v8, a1
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; CHECK-NEXT: vsll.vx v12, v12, a3
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; CHECK-NEXT: vor.vv v12, v18, v12
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; CHECK-NEXT: vsrl.vi v18, v8, 8
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; CHECK-NEXT: vand.vx v16, v16, a0
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; CHECK-NEXT: vand.vv v18, v18, v10
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; CHECK-NEXT: vor.vv v16, v18, v16
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; CHECK-NEXT: lui a1, 61681
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; CHECK-NEXT: lui a2, 209715
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; CHECK-NEXT: lui a3, 349525
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; CHECK-NEXT: addi a1, a1, -241
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; CHECK-NEXT: addi a2, a2, 819
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; CHECK-NEXT: addi a3, a3, 1365
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; CHECK-NEXT: vor.vv v14, v16, v14
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; CHECK-NEXT: vsetvli a4, zero, e32, m2, ta, ma
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; CHECK-NEXT: vmv.v.x v16, a1
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; CHECK-NEXT: vsetvli a1, zero, e64, m2, ta, ma
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; CHECK-NEXT: vand.vv v10, v8, v10
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; CHECK-NEXT: vand.vx v8, v8, a0
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; CHECK-NEXT: vsll.vi v8, v8, 24
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; CHECK-NEXT: vsll.vi v10, v10, 8
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; CHECK-NEXT: vor.vv v8, v8, v10
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; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma
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; CHECK-NEXT: vmv.v.x v10, a2
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; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma
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; CHECK-NEXT: vor.vv v8, v12, v8
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; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma
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; CHECK-NEXT: vmv.v.x v12, a3
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; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma
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; CHECK-NEXT: vor.vv v8, v8, v14
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; CHECK-NEXT: vsrl.vi v14, v8, 4
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; CHECK-NEXT: vand.vv v8, v8, v16
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; CHECK-NEXT: vand.vv v14, v14, v16
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; CHECK-NEXT: vsll.vi v8, v8, 4
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; CHECK-NEXT: vor.vv v8, v14, v8
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; CHECK-NEXT: vsrl.vi v14, v8, 2
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; CHECK-NEXT: vand.vv v8, v8, v10
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; CHECK-NEXT: vand.vv v10, v14, v10
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; CHECK-NEXT: vsll.vi v8, v8, 2
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; CHECK-NEXT: vor.vv v8, v10, v8
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; CHECK-NEXT: vsrl.vi v10, v8, 1
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; CHECK-NEXT: vand.vv v8, v8, v12
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; CHECK-NEXT: vand.vv v10, v10, v12
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; CHECK-NEXT: vadd.vv v8, v8, v8
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; CHECK-NEXT: vor.vv v8, v10, v8
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; CHECK-NEXT: vslidedown.vi v8, v8, 3
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; CHECK-NEXT: vmv.x.s a0, v8
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; CHECK-NEXT: addi sp, sp, 16
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; CHECK-NEXT: .cfi_def_cfa_offset 0
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; CHECK-NEXT: ret
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%1 = insertelement <vscale x 2 x i64> zeroinitializer, i64 3, i64 3
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%2 = tail call <vscale x 2 x i64> @llvm.bitreverse.nxv2i64(<vscale x 2 x i64> %1)
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%3 = extractelement <vscale x 2 x i64> %2, i32 3
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%4 = trunc i64 %3 to i32
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ret i32 %4
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}
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