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llvm-project/llvm/test/CodeGen
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Sjoerd Meijer 90ecb862a0 [AArch64] Rewrite (add, csel) to cinc 
Don't rewrite an add instruction with 2 SET_CC operands into a csel
instruction. The total instruction sequence uses an extra instruction and
register. Preventing this allows us to match a `(add, csel)` pattern and
rewrite this into a `cinc`.

Differential Revision: https://reviews.llvm.org/D98704
2021-03-18 08:49:27 +00:00
..
AArch64
[AArch64] Rewrite (add, csel) to cinc
2021-03-18 08:49:27 +00:00
AMDGPU
[DAG] TargetLowering::isBinOp() - add ISD::SSUBSAT/USUBSAT
2021-03-17 14:51:00 +00:00
ARC
…
ARM
[ARM] Use lrdsb for more thumb1 loads.
2021-03-17 15:29:02 +00:00
AVR
[AVR] Fix lifeness issues in the AVR backend
2021-03-04 14:04:39 +01:00
BPF
[BPF] Add support for floats and doubles
2021-03-05 15:10:11 +01:00
Generic
[PowerPC] Removing _massv place holder
2021-03-08 21:43:24 +00:00
Hexagon
[Hexagon] Improve stack address base reuse for HVX spills
2021-03-17 21:22:56 -05:00
Inputs
…
Lanai
…
M68k
[M68k] Fixed incorrect extract-section command substitution
2021-03-16 13:37:50 -07:00
Mips
Test cases for rem-seteq fold with illegal types
2021-03-12 16:28:04 +02:00
MIR
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
MSP430
…
NVPTX
[NVPTX] CUDA does provide malloc/free since compute capability 2.X
2021-03-15 22:45:56 -05:00
PowerPC
[NFC] [XCOFF] Update PowerPC readobj test case with expression
2021-03-17 16:02:50 +08:00
RISCV
[RISCV] Fix isel pattern of masked vmslt[u]
2021-03-17 20:18:11 -07:00
SPARC
[LegalizeTypes] Improve ExpandIntRes_XMULO codegen.
2021-03-01 09:54:32 -08:00
SystemZ
[SystemZ] Reimplement the i8/i16 compare-and-swap logic.
2021-03-03 14:04:32 -06:00
Thumb
[ARM] Use lrdsb for more thumb1 loads.
2021-03-17 15:29:02 +00:00
Thumb2
Test cases for rem-seteq fold with illegal types
2021-03-12 16:28:04 +02:00
VE
[test] Fix CodeGen/VE/Scalar tests
2021-03-02 15:30:44 -08:00
WebAssembly
[WebAssembly] Fix ExceptionInfo grouping again
2021-03-04 15:05:13 -08:00
WinCFGuard
…
WinEH
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X86
[X86][SSE] Add SSE2/SSE42 test coverage to urem combine tests
2021-03-17 19:58:03 +00:00
XCore
[CodeGen] Report a normal instead of fatal error for label redefinition
2021-03-09 10:54:41 +00:00