2946cd7010
to reflect the new license. We understand that people may be surprised that we're moving the header entirely to discuss the new license. We checked this carefully with the Foundation's lawyer and we believe this is the correct approach. Essentially, all code in the project is now made available by the LLVM project under our new license, so you will see that the license headers include that license only. Some of our contributors have contributed code under our old license, and accordingly, we have retained a copy of our old license notice in the top-level files in each project and repository. llvm-svn: 351636
158 lines
3.9 KiB
C++
158 lines
3.9 KiB
C++
//===-- RISCVBaseInfo.h - Top level definitions for RISCV MC ----*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains small standalone enum definitions for the RISCV target
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// useful for the compiler back-end and the MC libraries.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVBASEINFO_H
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#define LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVBASEINFO_H
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#include "MCTargetDesc/RISCVMCTargetDesc.h"
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#include "llvm/ADT/StringRef.h"
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#include "llvm/ADT/StringSwitch.h"
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#include "llvm/MC/SubtargetFeature.h"
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namespace llvm {
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// RISCVII - This namespace holds all of the target specific flags that
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// instruction info tracks. All definitions must match RISCVInstrFormats.td.
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namespace RISCVII {
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enum {
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InstFormatPseudo = 0,
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InstFormatR = 1,
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InstFormatR4 = 2,
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InstFormatI = 3,
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InstFormatS = 4,
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InstFormatB = 5,
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InstFormatU = 6,
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InstFormatJ = 7,
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InstFormatCR = 8,
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InstFormatCI = 9,
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InstFormatCSS = 10,
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InstFormatCIW = 11,
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InstFormatCL = 12,
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InstFormatCS = 13,
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InstFormatCA = 14,
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InstFormatCB = 15,
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InstFormatCJ = 16,
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InstFormatOther = 17,
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InstFormatMask = 31
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};
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enum {
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MO_None,
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MO_LO,
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MO_HI,
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MO_PCREL_HI,
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};
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} // namespace RISCVII
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// Describes the predecessor/successor bits used in the FENCE instruction.
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namespace RISCVFenceField {
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enum FenceField {
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I = 8,
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O = 4,
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R = 2,
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W = 1
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};
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}
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// Describes the supported floating point rounding mode encodings.
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namespace RISCVFPRndMode {
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enum RoundingMode {
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RNE = 0,
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RTZ = 1,
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RDN = 2,
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RUP = 3,
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RMM = 4,
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DYN = 7,
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Invalid
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};
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inline static StringRef roundingModeToString(RoundingMode RndMode) {
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switch (RndMode) {
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default:
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llvm_unreachable("Unknown floating point rounding mode");
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case RISCVFPRndMode::RNE:
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return "rne";
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case RISCVFPRndMode::RTZ:
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return "rtz";
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case RISCVFPRndMode::RDN:
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return "rdn";
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case RISCVFPRndMode::RUP:
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return "rup";
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case RISCVFPRndMode::RMM:
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return "rmm";
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case RISCVFPRndMode::DYN:
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return "dyn";
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}
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}
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inline static RoundingMode stringToRoundingMode(StringRef Str) {
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return StringSwitch<RoundingMode>(Str)
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.Case("rne", RISCVFPRndMode::RNE)
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.Case("rtz", RISCVFPRndMode::RTZ)
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.Case("rdn", RISCVFPRndMode::RDN)
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.Case("rup", RISCVFPRndMode::RUP)
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.Case("rmm", RISCVFPRndMode::RMM)
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.Case("dyn", RISCVFPRndMode::DYN)
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.Default(RISCVFPRndMode::Invalid);
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}
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inline static bool isValidRoundingMode(unsigned Mode) {
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switch (Mode) {
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default:
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return false;
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case RISCVFPRndMode::RNE:
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case RISCVFPRndMode::RTZ:
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case RISCVFPRndMode::RDN:
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case RISCVFPRndMode::RUP:
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case RISCVFPRndMode::RMM:
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case RISCVFPRndMode::DYN:
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return true;
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}
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}
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} // namespace RISCVFPRndMode
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namespace RISCVSysReg {
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struct SysReg {
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const char *Name;
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unsigned Encoding;
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// FIXME: add these additional fields when needed.
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// Privilege Access: Read, Write, Read-Only.
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// unsigned ReadWrite;
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// Privilege Mode: User, System or Machine.
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// unsigned Mode;
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// Check field name.
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// unsigned Extra;
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// Register number without the privilege bits.
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// unsigned Number;
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FeatureBitset FeaturesRequired;
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bool isRV32Only;
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bool haveRequiredFeatures(FeatureBitset ActiveFeatures) const {
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// Not in 32-bit mode.
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if (isRV32Only && ActiveFeatures[RISCV::Feature64Bit])
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return false;
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// No required feature associated with the system register.
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if (FeaturesRequired.none())
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return true;
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return (FeaturesRequired & ActiveFeatures) == FeaturesRequired;
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}
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};
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#define GET_SysRegsList_DECL
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#include "RISCVGenSystemOperands.inc"
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} // end namespace RISCVSysReg
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} // namespace llvm
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#endif
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