2946cd7010
to reflect the new license. We understand that people may be surprised that we're moving the header entirely to discuss the new license. We checked this carefully with the Foundation's lawyer and we believe this is the correct approach. Essentially, all code in the project is now made available by the LLVM project under our new license, so you will see that the license headers include that license only. Some of our contributors have contributed code under our old license, and accordingly, we have retained a copy of our old license notice in the top-level files in each project and repository. llvm-svn: 351636
183 lines
4.4 KiB
C++
183 lines
4.4 KiB
C++
//===- X86MacroFusion.cpp - X86 Macro Fusion ------------------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file This file contains the X86 implementation of the DAG scheduling
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/// mutation to pair instructions back to back.
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//
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//===----------------------------------------------------------------------===//
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#include "X86MacroFusion.h"
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#include "X86Subtarget.h"
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#include "llvm/CodeGen/MacroFusion.h"
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#include "llvm/CodeGen/TargetInstrInfo.h"
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using namespace llvm;
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/// Check if the instr pair, FirstMI and SecondMI, should be fused
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/// together. Given SecondMI, when FirstMI is unspecified, then check if
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/// SecondMI may be part of a fused pair at all.
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static bool shouldScheduleAdjacent(const TargetInstrInfo &TII,
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const TargetSubtargetInfo &TSI,
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const MachineInstr *FirstMI,
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const MachineInstr &SecondMI) {
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const X86Subtarget &ST = static_cast<const X86Subtarget&>(TSI);
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// Check if this processor supports macro-fusion.
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if (!ST.hasMacroFusion())
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return false;
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enum {
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FuseTest,
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FuseCmp,
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FuseInc
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} FuseKind;
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unsigned FirstOpcode = FirstMI
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? FirstMI->getOpcode()
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: static_cast<unsigned>(X86::INSTRUCTION_LIST_END);
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unsigned SecondOpcode = SecondMI.getOpcode();
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switch (SecondOpcode) {
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default:
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return false;
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case X86::JE_1:
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case X86::JNE_1:
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case X86::JL_1:
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case X86::JLE_1:
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case X86::JG_1:
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case X86::JGE_1:
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FuseKind = FuseInc;
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break;
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case X86::JB_1:
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case X86::JBE_1:
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case X86::JA_1:
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case X86::JAE_1:
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FuseKind = FuseCmp;
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break;
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case X86::JS_1:
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case X86::JNS_1:
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case X86::JP_1:
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case X86::JNP_1:
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case X86::JO_1:
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case X86::JNO_1:
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FuseKind = FuseTest;
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break;
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}
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switch (FirstOpcode) {
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default:
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return false;
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case X86::TEST8rr:
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case X86::TEST16rr:
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case X86::TEST32rr:
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case X86::TEST64rr:
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case X86::TEST8ri:
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case X86::TEST16ri:
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case X86::TEST32ri:
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case X86::TEST64ri32:
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case X86::TEST8mr:
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case X86::TEST16mr:
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case X86::TEST32mr:
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case X86::TEST64mr:
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case X86::AND16ri:
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case X86::AND16ri8:
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case X86::AND16rm:
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case X86::AND16rr:
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case X86::AND32ri:
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case X86::AND32ri8:
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case X86::AND32rm:
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case X86::AND32rr:
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case X86::AND64ri32:
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case X86::AND64ri8:
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case X86::AND64rm:
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case X86::AND64rr:
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case X86::AND8ri:
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case X86::AND8rm:
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case X86::AND8rr:
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return true;
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case X86::CMP16ri:
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case X86::CMP16ri8:
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case X86::CMP16rm:
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case X86::CMP16rr:
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case X86::CMP16mr:
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case X86::CMP32ri:
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case X86::CMP32ri8:
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case X86::CMP32rm:
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case X86::CMP32rr:
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case X86::CMP32mr:
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case X86::CMP64ri32:
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case X86::CMP64ri8:
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case X86::CMP64rm:
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case X86::CMP64rr:
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case X86::CMP64mr:
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case X86::CMP8ri:
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case X86::CMP8rm:
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case X86::CMP8rr:
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case X86::CMP8mr:
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case X86::ADD16ri:
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case X86::ADD16ri8:
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case X86::ADD16ri8_DB:
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case X86::ADD16ri_DB:
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case X86::ADD16rm:
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case X86::ADD16rr:
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case X86::ADD16rr_DB:
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case X86::ADD32ri:
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case X86::ADD32ri8:
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case X86::ADD32ri8_DB:
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case X86::ADD32ri_DB:
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case X86::ADD32rm:
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case X86::ADD32rr:
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case X86::ADD32rr_DB:
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case X86::ADD64ri32:
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case X86::ADD64ri32_DB:
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case X86::ADD64ri8:
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case X86::ADD64ri8_DB:
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case X86::ADD64rm:
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case X86::ADD64rr:
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case X86::ADD64rr_DB:
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case X86::ADD8ri:
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case X86::ADD8rm:
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case X86::ADD8rr:
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case X86::SUB16ri:
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case X86::SUB16ri8:
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case X86::SUB16rm:
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case X86::SUB16rr:
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case X86::SUB32ri:
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case X86::SUB32ri8:
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case X86::SUB32rm:
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case X86::SUB32rr:
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case X86::SUB64ri32:
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case X86::SUB64ri8:
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case X86::SUB64rm:
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case X86::SUB64rr:
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case X86::SUB8ri:
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case X86::SUB8rm:
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case X86::SUB8rr:
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return FuseKind == FuseCmp || FuseKind == FuseInc;
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case X86::INC16r:
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case X86::INC32r:
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case X86::INC64r:
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case X86::INC8r:
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case X86::DEC16r:
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case X86::DEC32r:
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case X86::DEC64r:
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case X86::DEC8r:
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return FuseKind == FuseInc;
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case X86::INSTRUCTION_LIST_END:
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return true;
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}
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}
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namespace llvm {
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std::unique_ptr<ScheduleDAGMutation>
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createX86MacroFusionDAGMutation () {
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return createBranchMacroFusionDAGMutation(shouldScheduleAdjacent);
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}
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} // end namespace llvm
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