d1592a966b
When attempting to replace a full vector constant load with an instruction that uses a smaller constant, check the scheduler model to ensure the instruction isn't slower. Throughput must not regress, but allow a small increase in latency based on how much constant data we're saving (I've used a simple estimate of 1 cycle per 128-bits of data saved). NOTE: this currently ignores hoisted constant loads where the slower instruction might be acceptable. Fixes #135998
29 lines
1.4 KiB
LLVM
29 lines
1.4 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=knl | FileCheck %s
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define <16 x i32> @test2(<16 x i32> %x) {
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; CHECK-LABEL: test2:
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; CHECK: ## %bb.0:
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; CHECK-NEXT: vpternlogd {{.*#+}} zmm1 = -1
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; CHECK-NEXT: vpaddd %zmm1, %zmm0, %zmm0
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; CHECK-NEXT: retq
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%res = add <16 x i32><i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1>, %x
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ret <16 x i32>%res
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}
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define <16 x float> @test3(<4 x float> %a) {
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; CHECK-LABEL: test3:
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; CHECK: ## %bb.0:
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; CHECK-NEXT: ## kill: def $xmm0 killed $xmm0 def $zmm0
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; CHECK-NEXT: vmovaps {{.*#+}} zmm2 = [0,1,2,3,4,18,16,7,8,9,10,11,12,13,14,15]
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; CHECK-NEXT: vxorps %xmm1, %xmm1, %xmm1
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; CHECK-NEXT: vpermt2ps %zmm0, %zmm2, %zmm1
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; CHECK-NEXT: vmovaps %zmm1, %zmm0
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; CHECK-NEXT: retq
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%b = extractelement <4 x float> %a, i32 2
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%c = insertelement <16 x float> <float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float undef, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>, float %b, i32 5
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%b1 = extractelement <4 x float> %a, i32 0
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%c1 = insertelement <16 x float> %c, float %b1, i32 6
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ret <16 x float>%c1
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}
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