d96529af3c
If a shl node leaves the upper half bits zero / undemanded, then see if we can profitably perform this with a half-width shl and a free trunc/zext. Followup to D146121 Reapplied - moved after the ShrinkDemandedOp call; reuse the existing KnownBits result; ensure that we only attempt this if all the upper bits are demanded; 547dc461225ba should address the remaining regressions that were noticed in the previous commit. Differential Revision: https://reviews.llvm.org/D155472
120 lines
4.0 KiB
LLVM
120 lines
4.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.2 | FileCheck %s
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define i1 @cmp_allbits_concat_i8(i8 %x, i8 %y) {
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; CHECK-LABEL: cmp_allbits_concat_i8:
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; CHECK: # %bb.0:
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; CHECK-NEXT: andl %esi, %edi
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; CHECK-NEXT: cmpb $-1, %dil
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; CHECK-NEXT: sete %al
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; CHECK-NEXT: retq
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%zx = zext i8 %x to i16
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%zy = zext i8 %y to i16
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%sh = shl i16 %zx, 8
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%or = or i16 %zy, %sh
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%r = icmp eq i16 %or, -1
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ret i1 %r
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}
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define i1 @cmp_anybits_concat_i32(i32 %x, i32 %y) {
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; CHECK-LABEL: cmp_anybits_concat_i32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: orl %esi, %edi
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; CHECK-NEXT: setne %al
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; CHECK-NEXT: retq
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%zx = zext i32 %x to i64
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%zy = zext i32 %y to i64
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%sh = shl i64 %zx, 32
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%or = or i64 %zy, %sh
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%r = icmp ne i64 %or, 0
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ret i1 %r
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}
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define i1 @cmp_anybits_concat_shl_shl_i16(i16 %x, i16 %y) {
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; CHECK-LABEL: cmp_anybits_concat_shl_shl_i16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movzwl %di, %eax
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; CHECK-NEXT: movzwl %si, %ecx
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; CHECK-NEXT: shll $8, %ecx
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; CHECK-NEXT: orl %eax, %ecx
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; CHECK-NEXT: sete %al
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; CHECK-NEXT: retq
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%zx = zext i16 %x to i64
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%zy = zext i16 %y to i64
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%sx = shl i64 %zx, 32
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%sy = shl i64 %zy, 8
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%or = or i64 %sx, %sy
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%r = icmp eq i64 %or, 0
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ret i1 %r
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}
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define i1 @cmp_anybits_concat_shl_shl_i16_commute(i16 %x, i16 %y) {
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; CHECK-LABEL: cmp_anybits_concat_shl_shl_i16_commute:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movzwl %di, %eax
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; CHECK-NEXT: movzwl %si, %ecx
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; CHECK-NEXT: shll $8, %ecx
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; CHECK-NEXT: orl %eax, %ecx
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; CHECK-NEXT: sete %al
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; CHECK-NEXT: retq
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%zx = zext i16 %x to i64
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%zy = zext i16 %y to i64
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%sx = shl i64 %zx, 32
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%sy = shl i64 %zy, 8
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%or = or i64 %sy, %sx
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%r = icmp eq i64 %or, 0
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ret i1 %r
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}
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; FIXME: Add vector support, but its only worth it if we can freely truncate the
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; concat'd vectors.
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define <16 x i8> @cmp_allbits_concat_v16i8(<16 x i8> %x, <16 x i8> %y) {
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; CHECK-LABEL: cmp_allbits_concat_v16i8:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movdqa %xmm1, %xmm2
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; CHECK-NEXT: punpcklbw {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1],xmm2[2],xmm0[2],xmm2[3],xmm0[3],xmm2[4],xmm0[4],xmm2[5],xmm0[5],xmm2[6],xmm0[6],xmm2[7],xmm0[7]
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; CHECK-NEXT: punpckhbw {{.*#+}} xmm1 = xmm1[8],xmm0[8],xmm1[9],xmm0[9],xmm1[10],xmm0[10],xmm1[11],xmm0[11],xmm1[12],xmm0[12],xmm1[13],xmm0[13],xmm1[14],xmm0[14],xmm1[15],xmm0[15]
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; CHECK-NEXT: pcmpeqd %xmm0, %xmm0
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; CHECK-NEXT: pcmpeqw %xmm0, %xmm1
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; CHECK-NEXT: pcmpeqw %xmm0, %xmm2
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; CHECK-NEXT: packsswb %xmm1, %xmm2
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; CHECK-NEXT: movdqa %xmm2, %xmm0
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; CHECK-NEXT: retq
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%zx = zext <16 x i8> %x to <16 x i16>
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%zy = zext <16 x i8> %y to <16 x i16>
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%sh = shl <16 x i16> %zx, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>
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%or = or <16 x i16> %zy, %sh
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%r = icmp eq <16 x i16> %or, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>
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%s = sext <16 x i1> %r to <16 x i8>
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ret <16 x i8> %s
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}
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define <2 x i64> @cmp_nobits_concat_v2i64(<2 x i64> %x, <2 x i64> %y) {
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; CHECK-LABEL: cmp_nobits_concat_v2i64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movq %xmm0, %rax
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; CHECK-NEXT: pextrq $1, %xmm0, %rcx
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; CHECK-NEXT: movq %xmm1, %rdx
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; CHECK-NEXT: pextrq $1, %xmm1, %rsi
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; CHECK-NEXT: xorl %edi, %edi
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; CHECK-NEXT: orq %rcx, %rsi
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; CHECK-NEXT: sete %dil
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; CHECK-NEXT: negq %rdi
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; CHECK-NEXT: movq %rdi, %xmm1
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; CHECK-NEXT: xorl %ecx, %ecx
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; CHECK-NEXT: orq %rax, %rdx
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; CHECK-NEXT: sete %cl
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; CHECK-NEXT: negq %rcx
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; CHECK-NEXT: movq %rcx, %xmm0
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; CHECK-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
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; CHECK-NEXT: retq
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%zx = zext <2 x i64> %x to <2 x i128>
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%zy = zext <2 x i64> %y to <2 x i128>
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%sh = shl <2 x i128> %zx, <i128 64, i128 64>
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%or = or <2 x i128> %zy, %sh
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%r = icmp eq <2 x i128> %or, zeroinitializer
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%s = sext <2 x i1> %r to <2 x i64>
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ret <2 x i64> %s
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}
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