9006bc8717
Despite currently being ignored with a warning, simd as a leaf in composite constructs behaves as expected when the construct does not contain a reduction. Enable it for those non-reduction constructs. --------- Signed-off-by: Kajetan Puchalski <kajetan.puchalski@arm.com>
39 lines
1.4 KiB
MLIR
39 lines
1.4 KiB
MLIR
// RUN: mlir-translate -mlir-to-llvmir %s | FileCheck %s
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// Check that omp.simd as a leaf of a composite construct still generates
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// the appropriate loop vectorization attribute.
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// CHECK-LABEL: define internal void @test_parallel_do_simd..omp_par
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// CHECK: omp.par.entry:
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// CHECK: omp.par.region:
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// CHECK: omp_loop.header:
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// CHECK: omp_loop.inc:
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// CHECK-NEXT: %omp_loop.next = add nuw i32 %omp_loop.iv, 1
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// CHECK-NEXT: br label %omp_loop.header, !llvm.loop ![[LOOP_ATTR:.*]]
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// CHECK: ![[LOOP_ATTR]] = distinct !{![[LOOP_ATTR]], ![[LPAR:.*]], ![[LVEC:.*]]}
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// CHECK: ![[LPAR]] = !{!"llvm.loop.parallel_accesses", ![[PAR_ACC:.*]]}
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// CHECK: ![[LVEC]] = !{!"llvm.loop.vectorize.enable", i1 true}
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llvm.func @test_parallel_do_simd() {
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%0 = llvm.mlir.constant(1 : i64) : i64
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%1 = llvm.alloca %0 x i32 {bindc_name = "i"} : (i64) -> !llvm.ptr
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%2 = llvm.mlir.constant(1000 : i32) : i32
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%3 = llvm.mlir.constant(1 : i32) : i32
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%4 = llvm.mlir.constant(1 : i64) : i64
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omp.parallel {
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%5 = llvm.mlir.constant(1 : i64) : i64
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%6 = llvm.alloca %5 x i32 {bindc_name = "i", pinned} : (i64) -> !llvm.ptr
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%7 = llvm.mlir.constant(1 : i64) : i64
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omp.wsloop {
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omp.simd {
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omp.loop_nest (%arg0) : i32 = (%3) to (%2) inclusive step (%3) {
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llvm.store %arg0, %6 : i32, !llvm.ptr
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omp.yield
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}
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} {omp.composite}
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} {omp.composite}
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omp.terminator
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}
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llvm.return
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}
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