1a14bfa022
As we introduced target triple environment amdgiz and amdgizcl, the address space values are no longer enums. We have to decide the value by target triple. The basic idea is to use struct AMDGPUAS to represent address space values. For address space values which are not depend on target triple, use static const members, so that they don't occupy extra memory space and is equivalent to a compile time constant. Since the struct is lightweight and cheap, it can be created on the fly at the point of usage. Or it can be added as member to a pass and created at the beginning of the run* function. Differential Revision: https://reviews.llvm.org/D31284 llvm-svn: 298846
204 lines
7.1 KiB
C++
204 lines
7.1 KiB
C++
//===-- AMDGPU.h - MachineFunction passes hw codegen --------------*- C++ -*-=//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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/// \file
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPU_H
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#define LLVM_LIB_TARGET_AMDGPU_AMDGPU_H
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#include "llvm/Target/TargetMachine.h"
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namespace llvm {
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class AMDGPUTargetMachine;
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class FunctionPass;
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class GCNTargetMachine;
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class ModulePass;
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class Pass;
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class Target;
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class TargetMachine;
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class PassRegistry;
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class Module;
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// R600 Passes
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FunctionPass *createR600VectorRegMerger(TargetMachine &tm);
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FunctionPass *createR600ExpandSpecialInstrsPass(TargetMachine &tm);
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FunctionPass *createR600EmitClauseMarkers();
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FunctionPass *createR600ClauseMergePass(TargetMachine &tm);
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FunctionPass *createR600Packetizer(TargetMachine &tm);
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FunctionPass *createR600ControlFlowFinalizer(TargetMachine &tm);
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FunctionPass *createAMDGPUCFGStructurizerPass();
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// SI Passes
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FunctionPass *createSITypeRewriter();
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FunctionPass *createSIAnnotateControlFlowPass();
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FunctionPass *createSIFoldOperandsPass();
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FunctionPass *createSIPeepholeSDWAPass();
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FunctionPass *createSILowerI1CopiesPass();
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FunctionPass *createSIShrinkInstructionsPass();
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FunctionPass *createSILoadStoreOptimizerPass(TargetMachine &tm);
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FunctionPass *createSIWholeQuadModePass();
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FunctionPass *createSIFixControlFlowLiveIntervalsPass();
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FunctionPass *createSIFixSGPRCopiesPass();
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FunctionPass *createSIDebuggerInsertNopsPass();
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FunctionPass *createSIInsertWaitsPass();
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FunctionPass *createAMDGPUCodeGenPreparePass(const GCNTargetMachine *TM = nullptr);
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ModulePass *createAMDGPUAnnotateKernelFeaturesPass(const TargetMachine *TM = nullptr);
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void initializeAMDGPUAnnotateKernelFeaturesPass(PassRegistry &);
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extern char &AMDGPUAnnotateKernelFeaturesID;
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ModulePass *createAMDGPULowerIntrinsicsPass();
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void initializeAMDGPULowerIntrinsicsPass(PassRegistry &);
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extern char &AMDGPULowerIntrinsicsID;
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void initializeSIFoldOperandsPass(PassRegistry &);
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extern char &SIFoldOperandsID;
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void initializeSIPeepholeSDWAPass(PassRegistry &);
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extern char &SIPeepholeSDWAID;
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void initializeSIShrinkInstructionsPass(PassRegistry&);
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extern char &SIShrinkInstructionsID;
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void initializeSIFixSGPRCopiesPass(PassRegistry &);
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extern char &SIFixSGPRCopiesID;
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void initializeSIFixVGPRCopiesPass(PassRegistry &);
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extern char &SIFixVGPRCopiesID;
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void initializeSILowerI1CopiesPass(PassRegistry &);
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extern char &SILowerI1CopiesID;
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void initializeSILoadStoreOptimizerPass(PassRegistry &);
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extern char &SILoadStoreOptimizerID;
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void initializeSIWholeQuadModePass(PassRegistry &);
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extern char &SIWholeQuadModeID;
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void initializeSILowerControlFlowPass(PassRegistry &);
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extern char &SILowerControlFlowID;
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void initializeSIInsertSkipsPass(PassRegistry &);
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extern char &SIInsertSkipsPassID;
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void initializeSIOptimizeExecMaskingPass(PassRegistry &);
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extern char &SIOptimizeExecMaskingID;
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// Passes common to R600 and SI
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FunctionPass *createAMDGPUPromoteAlloca(const TargetMachine *TM = nullptr);
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void initializeAMDGPUPromoteAllocaPass(PassRegistry&);
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extern char &AMDGPUPromoteAllocaID;
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Pass *createAMDGPUStructurizeCFGPass();
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FunctionPass *createAMDGPUISelDag(TargetMachine &TM,
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CodeGenOpt::Level OptLevel);
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ModulePass *createAMDGPUAlwaysInlinePass();
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ModulePass *createAMDGPUOpenCLImageTypeLoweringPass();
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FunctionPass *createAMDGPUAnnotateUniformValues();
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ModulePass* createAMDGPUUnifyMetadataPass();
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void initializeAMDGPUUnifyMetadataPass(PassRegistry&);
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extern char &AMDGPUUnifyMetadataID;
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void initializeSIFixControlFlowLiveIntervalsPass(PassRegistry&);
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extern char &SIFixControlFlowLiveIntervalsID;
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void initializeAMDGPUAnnotateUniformValuesPass(PassRegistry&);
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extern char &AMDGPUAnnotateUniformValuesPassID;
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void initializeAMDGPUCodeGenPreparePass(PassRegistry&);
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extern char &AMDGPUCodeGenPrepareID;
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void initializeSIAnnotateControlFlowPass(PassRegistry&);
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extern char &SIAnnotateControlFlowPassID;
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void initializeSIDebuggerInsertNopsPass(PassRegistry&);
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extern char &SIDebuggerInsertNopsID;
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void initializeSIInsertWaitsPass(PassRegistry&);
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extern char &SIInsertWaitsID;
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void initializeAMDGPUUnifyDivergentExitNodesPass(PassRegistry&);
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extern char &AMDGPUUnifyDivergentExitNodesID;
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ImmutablePass *createAMDGPUAAWrapperPass();
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void initializeAMDGPUAAWrapperPassPass(PassRegistry&);
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Target &getTheAMDGPUTarget();
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Target &getTheGCNTarget();
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namespace AMDGPU {
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enum TargetIndex {
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TI_CONSTDATA_START,
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TI_SCRATCH_RSRC_DWORD0,
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TI_SCRATCH_RSRC_DWORD1,
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TI_SCRATCH_RSRC_DWORD2,
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TI_SCRATCH_RSRC_DWORD3
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};
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}
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} // End namespace llvm
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/// OpenCL uses address spaces to differentiate between
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/// various memory regions on the hardware. On the CPU
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/// all of the address spaces point to the same memory,
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/// however on the GPU, each address space points to
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/// a separate piece of memory that is unique from other
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/// memory locations.
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struct AMDGPUAS {
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// The following address space values depend on the triple environment.
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unsigned PRIVATE_ADDRESS; ///< Address space for private memory.
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unsigned CONSTANT_ADDRESS; ///< Address space for constant memory (VTX2)
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unsigned FLAT_ADDRESS; ///< Address space for flat memory.
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unsigned REGION_ADDRESS; ///< Address space for region memory.
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// The maximum value for flat, generic, local, private, constant and region.
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const static unsigned MAX_COMMON_ADDRESS = 5;
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const static unsigned GLOBAL_ADDRESS = 1; ///< Address space for global memory (RAT0, VTX0).
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const static unsigned LOCAL_ADDRESS = 3; ///< Address space for local memory.
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const static unsigned PARAM_D_ADDRESS = 6; ///< Address space for direct addressible parameter memory (CONST0)
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const static unsigned PARAM_I_ADDRESS = 7; ///< Address space for indirect addressible parameter memory (VTX1)
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// Do not re-order the CONSTANT_BUFFER_* enums. Several places depend on this
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// order to be able to dynamically index a constant buffer, for example:
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//
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// ConstantBufferAS = CONSTANT_BUFFER_0 + CBIdx
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const static unsigned CONSTANT_BUFFER_0 = 8;
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const static unsigned CONSTANT_BUFFER_1 = 9;
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const static unsigned CONSTANT_BUFFER_2 = 10;
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const static unsigned CONSTANT_BUFFER_3 = 11;
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const static unsigned CONSTANT_BUFFER_4 = 12;
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const static unsigned CONSTANT_BUFFER_5 = 13;
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const static unsigned CONSTANT_BUFFER_6 = 14;
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const static unsigned CONSTANT_BUFFER_7 = 15;
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const static unsigned CONSTANT_BUFFER_8 = 16;
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const static unsigned CONSTANT_BUFFER_9 = 17;
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const static unsigned CONSTANT_BUFFER_10 = 18;
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const static unsigned CONSTANT_BUFFER_11 = 19;
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const static unsigned CONSTANT_BUFFER_12 = 20;
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const static unsigned CONSTANT_BUFFER_13 = 21;
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const static unsigned CONSTANT_BUFFER_14 = 22;
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const static unsigned CONSTANT_BUFFER_15 = 23;
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// Some places use this if the address space can't be determined.
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const static unsigned UNKNOWN_ADDRESS_SPACE = ~0u;
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};
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namespace llvm {
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namespace AMDGPU {
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AMDGPUAS getAMDGPUAS(const Module &M);
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AMDGPUAS getAMDGPUAS(const TargetMachine &TM);
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AMDGPUAS getAMDGPUAS(Triple T);
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} // namespace AMDGPU
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} // namespace llvm
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#endif
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