74b7abf154
Add a new `CreateIntrinsic` overload with no `Types`, useful for creating calls to non-overloaded intrinsics that don't need additional mangling.
526 lines
19 KiB
C++
526 lines
19 KiB
C++
//===-- AMDGPULowerKernelArguments.cpp ------------------------------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file This pass replaces accesses to kernel arguments with loads from
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/// offsets from the kernarg base pointer.
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//
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//===----------------------------------------------------------------------===//
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#include "AMDGPU.h"
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#include "GCNSubtarget.h"
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#include "llvm/Analysis/ValueTracking.h"
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#include "llvm/CodeGen/TargetPassConfig.h"
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#include "llvm/IR/Attributes.h"
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#include "llvm/IR/IRBuilder.h"
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#include "llvm/IR/IntrinsicsAMDGPU.h"
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#include "llvm/IR/MDBuilder.h"
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#include "llvm/Target/TargetMachine.h"
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#define DEBUG_TYPE "amdgpu-lower-kernel-arguments"
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using namespace llvm;
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namespace {
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class PreloadKernelArgInfo {
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private:
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Function &F;
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const GCNSubtarget &ST;
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unsigned NumFreeUserSGPRs;
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enum HiddenArg : unsigned {
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HIDDEN_BLOCK_COUNT_X,
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HIDDEN_BLOCK_COUNT_Y,
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HIDDEN_BLOCK_COUNT_Z,
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HIDDEN_GROUP_SIZE_X,
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HIDDEN_GROUP_SIZE_Y,
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HIDDEN_GROUP_SIZE_Z,
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HIDDEN_REMAINDER_X,
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HIDDEN_REMAINDER_Y,
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HIDDEN_REMAINDER_Z,
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END_HIDDEN_ARGS
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};
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// Stores information about a specific hidden argument.
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struct HiddenArgInfo {
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// Offset in bytes from the location in the kernearg segment pointed to by
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// the implicitarg pointer.
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uint8_t Offset;
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// The size of the hidden argument in bytes.
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uint8_t Size;
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// The name of the hidden argument in the kernel signature.
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const char *Name;
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};
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static constexpr HiddenArgInfo HiddenArgs[END_HIDDEN_ARGS] = {
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{0, 4, "_hidden_block_count_x"}, {4, 4, "_hidden_block_count_y"},
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{8, 4, "_hidden_block_count_z"}, {12, 2, "_hidden_group_size_x"},
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{14, 2, "_hidden_group_size_y"}, {16, 2, "_hidden_group_size_z"},
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{18, 2, "_hidden_remainder_x"}, {20, 2, "_hidden_remainder_y"},
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{22, 2, "_hidden_remainder_z"}};
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static HiddenArg getHiddenArgFromOffset(unsigned Offset) {
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for (unsigned I = 0; I < END_HIDDEN_ARGS; ++I)
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if (HiddenArgs[I].Offset == Offset)
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return static_cast<HiddenArg>(I);
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return END_HIDDEN_ARGS;
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}
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static Type *getHiddenArgType(LLVMContext &Ctx, HiddenArg HA) {
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if (HA < END_HIDDEN_ARGS)
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return Type::getIntNTy(Ctx, HiddenArgs[HA].Size * 8);
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llvm_unreachable("Unexpected hidden argument.");
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}
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static const char *getHiddenArgName(HiddenArg HA) {
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if (HA < END_HIDDEN_ARGS) {
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return HiddenArgs[HA].Name;
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}
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llvm_unreachable("Unexpected hidden argument.");
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}
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// Clones the function after adding implicit arguments to the argument list
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// and returns the new updated function. Preloaded implicit arguments are
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// added up to and including the last one that will be preloaded, indicated by
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// LastPreloadIndex. Currently preloading is only performed on the totality of
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// sequential data from the kernarg segment including implicit (hidden)
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// arguments. This means that all arguments up to the last preloaded argument
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// will also be preloaded even if that data is unused.
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Function *cloneFunctionWithPreloadImplicitArgs(unsigned LastPreloadIndex) {
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FunctionType *FT = F.getFunctionType();
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LLVMContext &Ctx = F.getParent()->getContext();
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SmallVector<Type *, 16> FTypes(FT->param_begin(), FT->param_end());
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for (unsigned I = 0; I <= LastPreloadIndex; ++I)
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FTypes.push_back(getHiddenArgType(Ctx, HiddenArg(I)));
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FunctionType *NFT =
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FunctionType::get(FT->getReturnType(), FTypes, FT->isVarArg());
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Function *NF =
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Function::Create(NFT, F.getLinkage(), F.getAddressSpace(), F.getName());
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NF->copyAttributesFrom(&F);
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NF->copyMetadata(&F, 0);
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NF->setIsNewDbgInfoFormat(F.IsNewDbgInfoFormat);
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F.getParent()->getFunctionList().insert(F.getIterator(), NF);
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NF->takeName(&F);
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NF->splice(NF->begin(), &F);
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Function::arg_iterator NFArg = NF->arg_begin();
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for (Argument &Arg : F.args()) {
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Arg.replaceAllUsesWith(&*NFArg);
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NFArg->takeName(&Arg);
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++NFArg;
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}
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AttrBuilder AB(Ctx);
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AB.addAttribute(Attribute::InReg);
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AB.addAttribute("amdgpu-hidden-argument");
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AttributeList AL = NF->getAttributes();
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for (unsigned I = 0; I <= LastPreloadIndex; ++I) {
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AL = AL.addParamAttributes(Ctx, NFArg->getArgNo(), AB);
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NFArg++->setName(getHiddenArgName(HiddenArg(I)));
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}
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NF->setAttributes(AL);
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F.replaceAllUsesWith(NF);
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F.setCallingConv(CallingConv::C);
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F.clearMetadata();
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return NF;
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}
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public:
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PreloadKernelArgInfo(Function &F, const GCNSubtarget &ST) : F(F), ST(ST) {
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setInitialFreeUserSGPRsCount();
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}
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// Returns the maximum number of user SGPRs that we have available to preload
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// arguments.
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void setInitialFreeUserSGPRsCount() {
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GCNUserSGPRUsageInfo UserSGPRInfo(F, ST);
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NumFreeUserSGPRs = UserSGPRInfo.getNumFreeUserSGPRs();
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}
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bool tryAllocPreloadSGPRs(unsigned AllocSize, uint64_t ArgOffset,
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uint64_t LastExplicitArgOffset) {
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// Check if this argument may be loaded into the same register as the
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// previous argument.
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if (ArgOffset - LastExplicitArgOffset < 4 &&
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!isAligned(Align(4), ArgOffset))
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return true;
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// Pad SGPRs for kernarg alignment.
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ArgOffset = alignDown(ArgOffset, 4);
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unsigned Padding = ArgOffset - LastExplicitArgOffset;
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unsigned PaddingSGPRs = alignTo(Padding, 4) / 4;
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unsigned NumPreloadSGPRs = alignTo(AllocSize, 4) / 4;
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if (NumPreloadSGPRs + PaddingSGPRs > NumFreeUserSGPRs)
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return false;
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NumFreeUserSGPRs -= (NumPreloadSGPRs + PaddingSGPRs);
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return true;
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}
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// Try to allocate SGPRs to preload implicit kernel arguments.
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void tryAllocImplicitArgPreloadSGPRs(uint64_t ImplicitArgsBaseOffset,
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uint64_t LastExplicitArgOffset,
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IRBuilder<> &Builder) {
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Function *ImplicitArgPtr = Intrinsic::getDeclarationIfExists(
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F.getParent(), Intrinsic::amdgcn_implicitarg_ptr);
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if (!ImplicitArgPtr)
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return;
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const DataLayout &DL = F.getParent()->getDataLayout();
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// Pair is the load and the load offset.
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SmallVector<std::pair<LoadInst *, unsigned>, 4> ImplicitArgLoads;
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for (auto *U : ImplicitArgPtr->users()) {
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Instruction *CI = dyn_cast<Instruction>(U);
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if (!CI || CI->getParent()->getParent() != &F)
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continue;
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for (auto *U : CI->users()) {
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int64_t Offset = 0;
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auto *Load = dyn_cast<LoadInst>(U); // Load from ImplicitArgPtr?
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if (!Load) {
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if (GetPointerBaseWithConstantOffset(U, Offset, DL) != CI)
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continue;
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Load = dyn_cast<LoadInst>(*U->user_begin()); // Load from GEP?
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}
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if (!Load || !Load->isSimple())
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continue;
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// FIXME: Expand to handle 64-bit implicit args and large merged loads.
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LLVMContext &Ctx = F.getParent()->getContext();
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Type *LoadTy = Load->getType();
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HiddenArg HA = getHiddenArgFromOffset(Offset);
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if (HA == END_HIDDEN_ARGS || LoadTy != getHiddenArgType(Ctx, HA))
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continue;
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ImplicitArgLoads.push_back(std::make_pair(Load, Offset));
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}
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}
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if (ImplicitArgLoads.empty())
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return;
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// Allocate loads in order of offset. We need to be sure that the implicit
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// argument can actually be preloaded.
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std::sort(ImplicitArgLoads.begin(), ImplicitArgLoads.end(), less_second());
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// If we fail to preload any implicit argument we know we don't have SGPRs
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// to preload any subsequent ones with larger offsets. Find the first
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// argument that we cannot preload.
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auto *PreloadEnd = std::find_if(
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ImplicitArgLoads.begin(), ImplicitArgLoads.end(),
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[&](const std::pair<LoadInst *, unsigned> &Load) {
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unsigned LoadSize = DL.getTypeStoreSize(Load.first->getType());
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unsigned LoadOffset = Load.second;
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if (!tryAllocPreloadSGPRs(LoadSize,
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LoadOffset + ImplicitArgsBaseOffset,
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LastExplicitArgOffset))
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return true;
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LastExplicitArgOffset =
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ImplicitArgsBaseOffset + LoadOffset + LoadSize;
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return false;
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});
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if (PreloadEnd == ImplicitArgLoads.begin())
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return;
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unsigned LastHiddenArgIndex = getHiddenArgFromOffset(PreloadEnd[-1].second);
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Function *NF = cloneFunctionWithPreloadImplicitArgs(LastHiddenArgIndex);
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assert(NF);
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for (const auto *I = ImplicitArgLoads.begin(); I != PreloadEnd; ++I) {
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LoadInst *LoadInst = I->first;
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unsigned LoadOffset = I->second;
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unsigned HiddenArgIndex = getHiddenArgFromOffset(LoadOffset);
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unsigned Index = NF->arg_size() - LastHiddenArgIndex + HiddenArgIndex - 1;
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Argument *Arg = NF->getArg(Index);
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LoadInst->replaceAllUsesWith(Arg);
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}
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}
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};
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class AMDGPULowerKernelArguments : public FunctionPass {
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public:
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static char ID;
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AMDGPULowerKernelArguments() : FunctionPass(ID) {}
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bool runOnFunction(Function &F) override;
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void getAnalysisUsage(AnalysisUsage &AU) const override {
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AU.addRequired<TargetPassConfig>();
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AU.setPreservesAll();
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}
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};
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} // end anonymous namespace
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// skip allocas
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static BasicBlock::iterator getInsertPt(BasicBlock &BB) {
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BasicBlock::iterator InsPt = BB.getFirstInsertionPt();
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for (BasicBlock::iterator E = BB.end(); InsPt != E; ++InsPt) {
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AllocaInst *AI = dyn_cast<AllocaInst>(&*InsPt);
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// If this is a dynamic alloca, the value may depend on the loaded kernargs,
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// so loads will need to be inserted before it.
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if (!AI || !AI->isStaticAlloca())
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break;
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}
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return InsPt;
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}
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static bool lowerKernelArguments(Function &F, const TargetMachine &TM) {
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CallingConv::ID CC = F.getCallingConv();
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if (CC != CallingConv::AMDGPU_KERNEL || F.arg_empty())
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return false;
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const GCNSubtarget &ST = TM.getSubtarget<GCNSubtarget>(F);
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LLVMContext &Ctx = F.getParent()->getContext();
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const DataLayout &DL = F.getDataLayout();
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BasicBlock &EntryBlock = *F.begin();
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IRBuilder<> Builder(&EntryBlock, getInsertPt(EntryBlock));
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const Align KernArgBaseAlign(16); // FIXME: Increase if necessary
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const uint64_t BaseOffset = ST.getExplicitKernelArgOffset();
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Align MaxAlign;
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// FIXME: Alignment is broken with explicit arg offset.;
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const uint64_t TotalKernArgSize = ST.getKernArgSegmentSize(F, MaxAlign);
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if (TotalKernArgSize == 0)
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return false;
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CallInst *KernArgSegment =
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Builder.CreateIntrinsic(Intrinsic::amdgcn_kernarg_segment_ptr, {},
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nullptr, F.getName() + ".kernarg.segment");
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KernArgSegment->addRetAttr(Attribute::NonNull);
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KernArgSegment->addRetAttr(
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Attribute::getWithDereferenceableBytes(Ctx, TotalKernArgSize));
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uint64_t ExplicitArgOffset = 0;
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// Preloaded kernel arguments must be sequential.
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bool InPreloadSequence = true;
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PreloadKernelArgInfo PreloadInfo(F, ST);
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for (Argument &Arg : F.args()) {
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const bool IsByRef = Arg.hasByRefAttr();
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Type *ArgTy = IsByRef ? Arg.getParamByRefType() : Arg.getType();
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MaybeAlign ParamAlign = IsByRef ? Arg.getParamAlign() : std::nullopt;
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Align ABITypeAlign = DL.getValueOrABITypeAlignment(ParamAlign, ArgTy);
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uint64_t Size = DL.getTypeSizeInBits(ArgTy);
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uint64_t AllocSize = DL.getTypeAllocSize(ArgTy);
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uint64_t EltOffset = alignTo(ExplicitArgOffset, ABITypeAlign) + BaseOffset;
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uint64_t LastExplicitArgOffset = ExplicitArgOffset;
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ExplicitArgOffset = alignTo(ExplicitArgOffset, ABITypeAlign) + AllocSize;
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// Guard against the situation where hidden arguments have already been
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// lowered and added to the kernel function signiture, i.e. in a situation
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// where this pass has run twice.
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if (Arg.hasAttribute("amdgpu-hidden-argument"))
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break;
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// Try to preload this argument into user SGPRs.
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if (Arg.hasInRegAttr() && InPreloadSequence && ST.hasKernargPreload() &&
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!Arg.getType()->isAggregateType())
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if (PreloadInfo.tryAllocPreloadSGPRs(AllocSize, EltOffset,
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LastExplicitArgOffset))
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continue;
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InPreloadSequence = false;
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if (Arg.use_empty())
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continue;
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// If this is byval, the loads are already explicit in the function. We just
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// need to rewrite the pointer values.
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if (IsByRef) {
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Value *ArgOffsetPtr = Builder.CreateConstInBoundsGEP1_64(
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Builder.getInt8Ty(), KernArgSegment, EltOffset,
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Arg.getName() + ".byval.kernarg.offset");
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Value *CastOffsetPtr =
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Builder.CreateAddrSpaceCast(ArgOffsetPtr, Arg.getType());
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Arg.replaceAllUsesWith(CastOffsetPtr);
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continue;
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}
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if (PointerType *PT = dyn_cast<PointerType>(ArgTy)) {
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// FIXME: Hack. We rely on AssertZext to be able to fold DS addressing
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// modes on SI to know the high bits are 0 so pointer adds don't wrap. We
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// can't represent this with range metadata because it's only allowed for
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// integer types.
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if ((PT->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS ||
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PT->getAddressSpace() == AMDGPUAS::REGION_ADDRESS) &&
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!ST.hasUsableDSOffset())
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continue;
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// FIXME: We can replace this with equivalent alias.scope/noalias
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// metadata, but this appears to be a lot of work.
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if (Arg.hasNoAliasAttr())
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continue;
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}
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auto *VT = dyn_cast<FixedVectorType>(ArgTy);
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bool IsV3 = VT && VT->getNumElements() == 3;
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bool DoShiftOpt = Size < 32 && !ArgTy->isAggregateType();
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VectorType *V4Ty = nullptr;
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int64_t AlignDownOffset = alignDown(EltOffset, 4);
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int64_t OffsetDiff = EltOffset - AlignDownOffset;
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Align AdjustedAlign = commonAlignment(
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KernArgBaseAlign, DoShiftOpt ? AlignDownOffset : EltOffset);
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Value *ArgPtr;
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Type *AdjustedArgTy;
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if (DoShiftOpt) { // FIXME: Handle aggregate types
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// Since we don't have sub-dword scalar loads, avoid doing an extload by
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// loading earlier than the argument address, and extracting the relevant
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// bits.
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// TODO: Update this for GFX12 which does have scalar sub-dword loads.
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//
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// Additionally widen any sub-dword load to i32 even if suitably aligned,
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// so that CSE between different argument loads works easily.
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ArgPtr = Builder.CreateConstInBoundsGEP1_64(
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Builder.getInt8Ty(), KernArgSegment, AlignDownOffset,
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Arg.getName() + ".kernarg.offset.align.down");
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AdjustedArgTy = Builder.getInt32Ty();
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} else {
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ArgPtr = Builder.CreateConstInBoundsGEP1_64(
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Builder.getInt8Ty(), KernArgSegment, EltOffset,
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Arg.getName() + ".kernarg.offset");
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AdjustedArgTy = ArgTy;
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}
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if (IsV3 && Size >= 32) {
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V4Ty = FixedVectorType::get(VT->getElementType(), 4);
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// Use the hack that clang uses to avoid SelectionDAG ruining v3 loads
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AdjustedArgTy = V4Ty;
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}
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LoadInst *Load =
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Builder.CreateAlignedLoad(AdjustedArgTy, ArgPtr, AdjustedAlign);
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Load->setMetadata(LLVMContext::MD_invariant_load, MDNode::get(Ctx, {}));
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MDBuilder MDB(Ctx);
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if (Arg.hasAttribute(Attribute::NoUndef))
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Load->setMetadata(LLVMContext::MD_noundef, MDNode::get(Ctx, {}));
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if (Arg.hasAttribute(Attribute::Range)) {
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const ConstantRange &Range =
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Arg.getAttribute(Attribute::Range).getValueAsConstantRange();
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Load->setMetadata(LLVMContext::MD_range,
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MDB.createRange(Range.getLower(), Range.getUpper()));
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}
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if (isa<PointerType>(ArgTy)) {
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if (Arg.hasNonNullAttr())
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Load->setMetadata(LLVMContext::MD_nonnull, MDNode::get(Ctx, {}));
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uint64_t DerefBytes = Arg.getDereferenceableBytes();
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if (DerefBytes != 0) {
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Load->setMetadata(
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LLVMContext::MD_dereferenceable,
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MDNode::get(Ctx,
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MDB.createConstant(
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ConstantInt::get(Builder.getInt64Ty(), DerefBytes))));
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}
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uint64_t DerefOrNullBytes = Arg.getDereferenceableOrNullBytes();
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if (DerefOrNullBytes != 0) {
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Load->setMetadata(
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LLVMContext::MD_dereferenceable_or_null,
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MDNode::get(Ctx,
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MDB.createConstant(ConstantInt::get(Builder.getInt64Ty(),
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DerefOrNullBytes))));
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}
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if (MaybeAlign ParamAlign = Arg.getParamAlign()) {
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Load->setMetadata(
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LLVMContext::MD_align,
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MDNode::get(Ctx, MDB.createConstant(ConstantInt::get(
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Builder.getInt64Ty(), ParamAlign->value()))));
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}
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}
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// TODO: Convert noalias arg to !noalias
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if (DoShiftOpt) {
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Value *ExtractBits = OffsetDiff == 0 ?
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Load : Builder.CreateLShr(Load, OffsetDiff * 8);
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IntegerType *ArgIntTy = Builder.getIntNTy(Size);
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Value *Trunc = Builder.CreateTrunc(ExtractBits, ArgIntTy);
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Value *NewVal = Builder.CreateBitCast(Trunc, ArgTy,
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Arg.getName() + ".load");
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Arg.replaceAllUsesWith(NewVal);
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} else if (IsV3) {
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Value *Shuf = Builder.CreateShuffleVector(Load, ArrayRef<int>{0, 1, 2},
|
|
Arg.getName() + ".load");
|
|
Arg.replaceAllUsesWith(Shuf);
|
|
} else {
|
|
Load->setName(Arg.getName() + ".load");
|
|
Arg.replaceAllUsesWith(Load);
|
|
}
|
|
}
|
|
|
|
KernArgSegment->addRetAttr(
|
|
Attribute::getWithAlignment(Ctx, std::max(KernArgBaseAlign, MaxAlign)));
|
|
|
|
if (InPreloadSequence) {
|
|
uint64_t ImplicitArgsBaseOffset =
|
|
alignTo(ExplicitArgOffset, ST.getAlignmentForImplicitArgPtr()) +
|
|
BaseOffset;
|
|
PreloadInfo.tryAllocImplicitArgPreloadSGPRs(ImplicitArgsBaseOffset,
|
|
ExplicitArgOffset, Builder);
|
|
}
|
|
|
|
return true;
|
|
}
|
|
|
|
bool AMDGPULowerKernelArguments::runOnFunction(Function &F) {
|
|
auto &TPC = getAnalysis<TargetPassConfig>();
|
|
const TargetMachine &TM = TPC.getTM<TargetMachine>();
|
|
return lowerKernelArguments(F, TM);
|
|
}
|
|
|
|
INITIALIZE_PASS_BEGIN(AMDGPULowerKernelArguments, DEBUG_TYPE,
|
|
"AMDGPU Lower Kernel Arguments", false, false)
|
|
INITIALIZE_PASS_END(AMDGPULowerKernelArguments, DEBUG_TYPE, "AMDGPU Lower Kernel Arguments",
|
|
false, false)
|
|
|
|
char AMDGPULowerKernelArguments::ID = 0;
|
|
|
|
FunctionPass *llvm::createAMDGPULowerKernelArgumentsPass() {
|
|
return new AMDGPULowerKernelArguments();
|
|
}
|
|
|
|
PreservedAnalyses
|
|
AMDGPULowerKernelArgumentsPass::run(Function &F, FunctionAnalysisManager &AM) {
|
|
bool Changed = lowerKernelArguments(F, TM);
|
|
if (Changed) {
|
|
// TODO: Preserves a lot more.
|
|
PreservedAnalyses PA;
|
|
PA.preserveSet<CFGAnalyses>();
|
|
return PA;
|
|
}
|
|
|
|
return PreservedAnalyses::all();
|
|
}
|