fe6fb910df
clang -fexperimental-relative-c++-abi-vtables might generate `@plt` and `@gotpcrel` specifiers in data directives. The syntax is not used in humand-written assembly code, and is not supported by GNU assembler. Note: the `@plt` in `.word foo@plt` is different from the legacy `call func@plt` (where `@plt` is simply ignored). The `@plt` syntax was selected was simply due to a quirk of AsmParser: the syntax was supported by all targets until I updated it to be an opt-in feature in a0671758eb6e52a758bd1b096a9b421eec60204c RISC-V favors the `%specifier(expr)` syntax following MIPS and Sparc, and we should follow this convention. This PR adds support for `.word %pltpcrel(foo+offset)` and `.word %gotpcrel(foo)`, and drops `@plt` and `@gotpcrel`. * MCValue::SymA can no longer have a SymbolVariant. Add an assert similar to that of AArch64ELFObjectWriter.cpp before https://reviews.llvm.org/D81446 (see my analysis at https://maskray.me/blog/2025-03-16-relocation-generation-in-assemblers if intrigued) * `jump foo@plt, x31` now has a different diagnostic. Pull Request: https://github.com/llvm/llvm-project/pull/132569
82 lines
2.7 KiB
C++
82 lines
2.7 KiB
C++
//===- R600MCInstLower.cpp - Lower R600 MachineInstr to an MCInst ---------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// Code to lower R600 MachineInstrs to their corresponding MCInst.
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//
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//===----------------------------------------------------------------------===//
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//
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#include "AMDGPUMCInstLower.h"
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#include "MCTargetDesc/R600MCTargetDesc.h"
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#include "R600AsmPrinter.h"
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#include "R600Subtarget.h"
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#include "llvm/CodeGen/MachineOperand.h"
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#include "llvm/MC/MCContext.h"
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#include "llvm/MC/MCExpr.h"
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namespace {
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class R600MCInstLower : public AMDGPUMCInstLower {
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public:
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R600MCInstLower(MCContext &ctx, const R600Subtarget &ST,
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const AsmPrinter &AP);
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/// Lower a MachineInstr to an MCInst
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void lower(const MachineInstr *MI, MCInst &OutMI) const;
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};
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} // namespace
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R600MCInstLower::R600MCInstLower(MCContext &Ctx, const R600Subtarget &ST,
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const AsmPrinter &AP)
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: AMDGPUMCInstLower(Ctx, ST, AP) {}
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void R600MCInstLower::lower(const MachineInstr *MI, MCInst &OutMI) const {
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OutMI.setOpcode(MI->getOpcode());
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for (const MachineOperand &MO : MI->explicit_operands()) {
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MCOperand MCOp;
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lowerOperand(MO, MCOp);
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OutMI.addOperand(MCOp);
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}
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}
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void R600AsmPrinter::emitInstruction(const MachineInstr *MI) {
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R600_MC::verifyInstructionPredicates(MI->getOpcode(),
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getSubtargetInfo().getFeatureBits());
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const R600Subtarget &STI = MF->getSubtarget<R600Subtarget>();
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R600MCInstLower MCInstLowering(OutContext, STI, *this);
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StringRef Err;
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if (!STI.getInstrInfo()->verifyInstruction(*MI, Err)) {
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LLVMContext &C = MI->getParent()->getParent()->getFunction().getContext();
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C.emitError("Illegal instruction detected: " + Err);
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MI->print(errs());
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}
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if (MI->isBundle()) {
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const MachineBasicBlock *MBB = MI->getParent();
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MachineBasicBlock::const_instr_iterator I = ++MI->getIterator();
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while (I != MBB->instr_end() && I->isInsideBundle()) {
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emitInstruction(&*I);
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++I;
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}
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} else {
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MCInst TmpInst;
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MCInstLowering.lower(MI, TmpInst);
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EmitToStreamer(*OutStreamer, TmpInst);
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}
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}
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const MCExpr *R600AsmPrinter::lowerConstant(const Constant *CV,
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const Constant *BaseCV,
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uint64_t Offset) {
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if (const MCExpr *E = lowerAddrSpaceCast(TM, CV, OutContext))
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return E;
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return AsmPrinter::lowerConstant(CV, BaseCV, Offset);
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}
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