71935281e0
DenseSet, SmallPtrSet, SmallSet, SetVector, and StringSet recently gained C++23-style insert_range. This patch replaces: Dest.insert(Src.begin(), Src.end()); with: Dest.insert_range(Src); This patch does not touch custom begin like succ_begin for now.
257 lines
11 KiB
C++
257 lines
11 KiB
C++
//===- SPIRVModuleAnalysis.h - analysis of global instrs & regs -*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// The analysis collects instructions that should be output at the module level
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// and performs the global register numbering.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_SPIRV_SPIRVMODULEANALYSIS_H
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#define LLVM_LIB_TARGET_SPIRV_SPIRVMODULEANALYSIS_H
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#include "MCTargetDesc/SPIRVBaseInfo.h"
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#include "SPIRVGlobalRegistry.h"
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#include "SPIRVUtils.h"
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#include "llvm/ADT/DenseMap.h"
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#include "llvm/ADT/SmallSet.h"
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#include "llvm/ADT/SmallVector.h"
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namespace llvm {
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class SPIRVSubtarget;
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class MachineFunction;
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class MachineModuleInfo;
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namespace SPIRV {
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// The enum contains logical module sections for the instruction collection.
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enum ModuleSectionType {
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// MB_Capabilities, MB_Extensions, MB_ExtInstImports, MB_MemoryModel,
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MB_EntryPoints, // All OpEntryPoint instructions (if any).
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// MB_ExecutionModes, MB_DebugSourceAndStrings,
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MB_DebugNames, // All OpName and OpMemberName intrs.
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MB_DebugStrings, // All OpString intrs.
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MB_DebugModuleProcessed, // All OpModuleProcessed instructions.
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MB_AliasingInsts, // SPV_INTEL_memory_access_aliasing instructions.
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MB_Annotations, // OpDecorate, OpMemberDecorate etc.
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MB_TypeConstVars, // OpTypeXXX, OpConstantXXX, and global OpVariables.
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MB_NonSemanticGlobalDI, // OpExtInst with e.g. DebugSource, DebugTypeBasic.
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MB_ExtFuncDecls, // OpFunction etc. to declare for external funcs.
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NUM_MODULE_SECTIONS // Total number of sections requiring basic blocks.
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};
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struct Requirements {
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const bool IsSatisfiable;
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const std::optional<Capability::Capability> Cap;
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const ExtensionList Exts;
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const VersionTuple MinVer; // 0 if no min version is required.
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const VersionTuple MaxVer; // 0 if no max version is required.
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Requirements(bool IsSatisfiable = false,
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std::optional<Capability::Capability> Cap = {},
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ExtensionList Exts = {}, VersionTuple MinVer = VersionTuple(),
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VersionTuple MaxVer = VersionTuple())
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: IsSatisfiable(IsSatisfiable), Cap(Cap), Exts(Exts), MinVer(MinVer),
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MaxVer(MaxVer) {}
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Requirements(Capability::Capability Cap) : Requirements(true, {Cap}) {}
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};
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struct RequirementHandler {
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private:
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CapabilityList MinimalCaps;
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// AllCaps and AvailableCaps are related but different. AllCaps is a subset of
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// AvailableCaps. AvailableCaps is the complete set of capabilities that are
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// available to the current target. AllCaps is the set of capabilities that
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// are required by the current module.
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SmallSet<Capability::Capability, 8> AllCaps;
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DenseSet<unsigned> AvailableCaps;
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SmallSet<Extension::Extension, 4> AllExtensions;
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VersionTuple MinVersion; // 0 if no min version is defined.
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VersionTuple MaxVersion; // 0 if no max version is defined.
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// Add capabilities to AllCaps, recursing through their implicitly declared
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// capabilities too.
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void recursiveAddCapabilities(const CapabilityList &ToPrune);
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void initAvailableCapabilitiesForOpenCL(const SPIRVSubtarget &ST);
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void initAvailableCapabilitiesForVulkan(const SPIRVSubtarget &ST);
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public:
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RequirementHandler() {}
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void clear() {
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MinimalCaps.clear();
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AllCaps.clear();
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AvailableCaps.clear();
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AllExtensions.clear();
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MinVersion = VersionTuple();
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MaxVersion = VersionTuple();
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}
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const CapabilityList &getMinimalCapabilities() const { return MinimalCaps; }
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const SmallSet<Extension::Extension, 4> &getExtensions() const {
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return AllExtensions;
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}
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// Add a list of capabilities, ensuring AllCaps captures all the implicitly
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// declared capabilities, and MinimalCaps has the minimal set of required
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// capabilities (so all implicitly declared ones are removed).
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void addCapabilities(const CapabilityList &ToAdd);
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void addCapability(Capability::Capability ToAdd) { addCapabilities({ToAdd}); }
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void addExtensions(const ExtensionList &ToAdd) {
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AllExtensions.insert_range(ToAdd);
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}
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void addExtension(Extension::Extension ToAdd) { AllExtensions.insert(ToAdd); }
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// Add the given requirements to the lists. If constraints conflict, or these
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// requirements cannot be satisfied, then abort the compilation.
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void addRequirements(const Requirements &Req);
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// Get requirement and add it to the list.
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void getAndAddRequirements(SPIRV::OperandCategory::OperandCategory Category,
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uint32_t i, const SPIRVSubtarget &ST);
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// Check if all the requirements can be satisfied for the given subtarget, and
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// if not abort compilation.
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void checkSatisfiable(const SPIRVSubtarget &ST) const;
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void initAvailableCapabilities(const SPIRVSubtarget &ST);
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// Add the given capabilities to available and all their implicitly defined
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// capabilities too.
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void addAvailableCaps(const CapabilityList &ToAdd);
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bool isCapabilityAvailable(Capability::Capability Cap) const {
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return AvailableCaps.contains(Cap);
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}
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// Remove capability ToRemove, but only if IfPresent is present.
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void removeCapabilityIf(const Capability::Capability ToRemove,
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const Capability::Capability IfPresent);
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};
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using InstrList = SmallVector<const MachineInstr *>;
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// Maps a local register to the corresponding global alias.
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using LocalToGlobalRegTable = std::map<Register, MCRegister>;
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using RegisterAliasMapTy =
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std::map<const MachineFunction *, LocalToGlobalRegTable>;
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// The struct contains results of the module analysis and methods
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// to access them.
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struct ModuleAnalysisInfo {
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RequirementHandler Reqs;
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MemoryModel::MemoryModel Mem;
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AddressingModel::AddressingModel Addr;
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SourceLanguage::SourceLanguage SrcLang;
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unsigned SrcLangVersion;
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StringSet<> SrcExt;
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// Maps ExtInstSet to corresponding ID register.
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DenseMap<unsigned, MCRegister> ExtInstSetMap;
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// Contains the list of all global OpVariables in the module.
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SmallVector<const MachineInstr *, 4> GlobalVarList;
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// Maps functions to corresponding function ID registers.
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DenseMap<const Function *, MCRegister> FuncMap;
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// The set contains machine instructions which are necessary
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// for correct MIR but will not be emitted in function bodies.
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DenseSet<const MachineInstr *> InstrsToDelete;
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// The table contains global aliases of local registers for each machine
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// function. The aliases are used to substitute local registers during
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// code emission.
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RegisterAliasMapTy RegisterAliasTable;
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// The counter holds the maximum ID we have in the module.
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unsigned MaxID;
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// The array contains lists of MIs for each module section.
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InstrList MS[NUM_MODULE_SECTIONS];
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// The table maps MBB number to SPIR-V unique ID register.
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DenseMap<std::pair<const MachineFunction *, int>, MCRegister> BBNumToRegMap;
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MCRegister getFuncReg(const Function *F) {
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assert(F && "Function is null");
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auto FuncPtrRegPair = FuncMap.find(F);
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return FuncPtrRegPair == FuncMap.end() ? MCRegister()
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: FuncPtrRegPair->second;
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}
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MCRegister getExtInstSetReg(unsigned SetNum) { return ExtInstSetMap[SetNum]; }
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InstrList &getMSInstrs(unsigned MSType) { return MS[MSType]; }
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void setSkipEmission(const MachineInstr *MI) { InstrsToDelete.insert(MI); }
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bool getSkipEmission(const MachineInstr *MI) {
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return InstrsToDelete.contains(MI);
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}
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void setRegisterAlias(const MachineFunction *MF, Register Reg,
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MCRegister AliasReg) {
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RegisterAliasTable[MF][Reg] = AliasReg;
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}
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MCRegister getRegisterAlias(const MachineFunction *MF, Register Reg) {
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auto &RegTable = RegisterAliasTable[MF];
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auto RI = RegTable.find(Reg);
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if (RI == RegTable.end()) {
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return MCRegister();
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}
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return RI->second;
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}
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bool hasRegisterAlias(const MachineFunction *MF, Register Reg) {
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auto RI = RegisterAliasTable.find(MF);
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if (RI == RegisterAliasTable.end())
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return false;
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return RI->second.find(Reg) != RI->second.end();
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}
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unsigned getNextID() { return MaxID++; }
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MCRegister getNextIDRegister() {
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return MCRegister((1U << 31) | getNextID());
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}
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bool hasMBBRegister(const MachineBasicBlock &MBB) {
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auto Key = std::make_pair(MBB.getParent(), MBB.getNumber());
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return BBNumToRegMap.contains(Key);
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}
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// Convert MBB's number to corresponding ID register.
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MCRegister getOrCreateMBBRegister(const MachineBasicBlock &MBB) {
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auto Key = std::make_pair(MBB.getParent(), MBB.getNumber());
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auto [It, Inserted] = BBNumToRegMap.try_emplace(Key);
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if (Inserted)
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It->second = getNextIDRegister();
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return It->second;
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}
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};
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} // namespace SPIRV
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using InstrSignature = SmallVector<size_t>;
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using InstrTraces = std::set<InstrSignature>;
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using InstrGRegsMap = std::map<SmallVector<size_t>, unsigned>;
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struct SPIRVModuleAnalysis : public ModulePass {
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static char ID;
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public:
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SPIRVModuleAnalysis() : ModulePass(ID) {}
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bool runOnModule(Module &M) override;
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void getAnalysisUsage(AnalysisUsage &AU) const override;
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static struct SPIRV::ModuleAnalysisInfo MAI;
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private:
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void setBaseInfo(const Module &M);
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void collectFuncNames(MachineInstr &MI, const Function *F);
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void processOtherInstrs(const Module &M);
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void numberRegistersGlobally(const Module &M);
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// analyze dependencies to collect module scope definitions
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void collectDeclarations(const Module &M);
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void visitDecl(const MachineRegisterInfo &MRI, InstrGRegsMap &SignatureToGReg,
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std::map<const Value *, unsigned> &GlobalToGReg,
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const MachineFunction *MF, const MachineInstr &MI);
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MCRegister handleVariable(const MachineFunction *MF, const MachineInstr &MI,
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std::map<const Value *, unsigned> &GlobalToGReg);
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MCRegister handleTypeDeclOrConstant(const MachineInstr &MI,
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InstrGRegsMap &SignatureToGReg);
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MCRegister
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handleFunctionOrParameter(const MachineFunction *MF, const MachineInstr &MI,
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std::map<const Value *, unsigned> &GlobalToGReg,
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bool &IsFunDef);
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void visitFunPtrUse(Register OpReg, InstrGRegsMap &SignatureToGReg,
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std::map<const Value *, unsigned> &GlobalToGReg,
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const MachineFunction *MF, const MachineInstr &MI);
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bool isDeclSection(const MachineRegisterInfo &MRI, const MachineInstr &MI);
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const SPIRVSubtarget *ST;
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SPIRVGlobalRegistry *GR;
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const SPIRVInstrInfo *TII;
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MachineModuleInfo *MMI;
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};
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} // namespace llvm
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#endif // LLVM_LIB_TARGET_SPIRV_SPIRVMODULEANALYSIS_H
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