shylie/llvm-project
1
0
Fork 0
Code Issues Pull Requests Actions 6 Packages Projects Releases Wiki Activity
llvm-project/llvm/test/CodeGen/MIR/AMDGPU
History
Sebastian Neubauer 8214982b50 [AMDGPU] Implement mir parseCustomPseudoSourceValue 
Allow parsing generated mir with custom pseudo source value tokens.
Also rename pseudo source values to have more meaningful names.

Relands ba7dcd8542ab, which had memory leaks.

Differential Revision: https://reviews.llvm.org/D95215
2021-01-22 11:24:08 +01:00
..
custom-pseudo-source-values.ll
[AMDGPU] Implement mir parseCustomPseudoSourceValue
2021-01-22 11:24:08 +01:00
expected-target-index-name.mir
…
intrinsics.mir
…
invalid-target-index-operand.mir
…
lit.local.cfg
…
llc-target-cpu-attr-from-cmdline-ir.mir
Revert "Revert "[AMDGPU] Reorganize GCN subtarget features for unaligned access""
2020-11-11 14:40:14 +00:00
llc-target-cpu-attr-from-cmdline.mir
Revert "Revert "[AMDGPU] Reorganize GCN subtarget features for unaligned access""
2020-11-11 14:40:14 +00:00
load-store-opt-dlc.mir
…
machine-function-info-dynlds-align-invalid-case.mir
[amdgpu] Add codegen support for HIP dynamic shared memory.
2020-08-20 21:29:18 -04:00
machine-function-info-no-ir.mir
AMDGPU: Add occupancy to serialized MachineFunctionInfo
2021-01-21 09:21:00 -05:00
machine-function-info-register-parse-error1.mir
[AMDGPU] Avoid hard-coded line numbers in error message checks
2020-04-23 21:06:09 +01:00
machine-function-info-register-parse-error2.mir
[AMDGPU] Avoid hard-coded line numbers in error message checks
2020-04-23 21:06:09 +01:00
machine-function-info.ll
AMDGPU: Add occupancy to serialized MachineFunctionInfo
2021-01-21 09:21:00 -05:00
mfi-frame-offset-reg-class.mir
[AMDGPU] Avoid hard-coded line numbers in error message checks
2020-04-23 21:06:09 +01:00
mfi-parse-error-frame-offset-reg.mir
[AMDGPU] Avoid hard-coded line numbers in error message checks
2020-04-23 21:06:09 +01:00
mfi-parse-error-scratch-rsrc-reg.mir
[AMDGPU] Avoid hard-coded line numbers in error message checks
2020-04-23 21:06:09 +01:00
mfi-parse-error-stack-ptr-offset-reg.mir
[AMDGPU] Avoid hard-coded line numbers in error message checks
2020-04-23 21:06:09 +01:00
mfi-scratch-rsrc-reg-reg-class.mir
[AMDGPU] Avoid hard-coded line numbers in error message checks
2020-04-23 21:06:09 +01:00
mfi-stack-ptr-offset-reg-class.mir
[AMDGPU] Avoid hard-coded line numbers in error message checks
2020-04-23 21:06:09 +01:00
mir-canon-multi.mir
[MIRVRegNamer] Experimental MachineInstr stable hashing (Fowler-Noll-Vo)
2020-09-03 16:13:09 -04:00
mircanon-memoperands.mir
[MIRVRegNamer] Experimental MachineInstr stable hashing (Fowler-Noll-Vo)
2020-09-03 16:13:09 -04:00
parse-order-reserved-regs.mir
[MIRVRegNamer] Experimental MachineInstr stable hashing (Fowler-Noll-Vo)
2020-09-03 16:13:09 -04:00
stack-id-assert.mir
[MIR] Fix out of bounds access in MIRPrinter.
2020-10-29 14:35:06 +03:00
stack-id.mir
…
subreg-def-is-not-ssa.mir
MIR: Infer not-SSA for subregister defs
2020-08-27 16:56:16 -04:00
syncscopes.mir
…
target-flags.mir
[AMDGPU] Fix offset for REL32_HI relocs
2020-09-02 10:55:55 +01:00
target-index-operands.mir
…