e7dc083a41
It turns our that the BranchFolder and IfCvt does not like unanalyzable branches that fall-through. This means that removing the unconditional branches from the end of tail predicated instruction can run into asserts and verifier issues. This effectively reverts 372eb2bbb6fb903ce76266e659dfefbaee67722b, but adds handling to t2DoLoopEndDec which are not branches, so can be safely skipped.
152 lines
6.2 KiB
LLVM
152 lines
6.2 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=thumbv8.1m.main-none-eabi -mattr=+mve --verify-machineinstrs %s -o - | FileCheck %s
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define void @simple(i32* nocapture readonly %x, i32* nocapture readnone %y, i32* nocapture %z, i32 %m, i32 %n) {
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; CHECK-LABEL: simple:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: .save {r7, lr}
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; CHECK-NEXT: push {r7, lr}
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; CHECK-NEXT: ldr r1, [sp, #8]
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; CHECK-NEXT: mov r12, r3
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; CHECK-NEXT: movs r3, #0
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; CHECK-NEXT: add.w lr, r1, #3
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; CHECK-NEXT: cmp.w r3, lr, lsr #2
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; CHECK-NEXT: beq .LBB0_3
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; CHECK-NEXT: @ %bb.1: @ %do.body.preheader
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; CHECK-NEXT: dlstp.32 lr, r1
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; CHECK-NEXT: .LBB0_2: @ %do.body
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; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: vldrw.u32 q0, [r0], #16
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; CHECK-NEXT: vaddva.s32 r12, q0
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; CHECK-NEXT: letp lr, .LBB0_2
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; CHECK-NEXT: .LBB0_3: @ %if.end
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; CHECK-NEXT: str.w r12, [r2]
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; CHECK-NEXT: pop {r7, pc}
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entry:
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%add = add i32 %n, 3
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%div = lshr i32 %add, 2
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%cmp.not = icmp eq i32 %div, 0
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br i1 %cmp.not, label %if.end, label %do.body
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do.body: ; preds = %entry, %do.body
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%n.addr.0 = phi i32 [ %sub, %do.body ], [ %n, %entry ]
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%count.0 = phi i32 [ %sub3, %do.body ], [ %div, %entry ]
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%s.0 = phi i32 [ %add2, %do.body ], [ %m, %entry ]
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%x.addr.0 = phi i32* [ %add.ptr, %do.body ], [ %x, %entry ]
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%0 = tail call <4 x i1> @llvm.arm.mve.vctp32(i32 %n.addr.0)
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%1 = bitcast i32* %x.addr.0 to <4 x i32>*
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%2 = load <4 x i32>, <4 x i32>* %1, align 4
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%3 = tail call i32 @llvm.arm.mve.addv.predicated.v4i32.v4i1(<4 x i32> %2, i32 0, <4 x i1> %0)
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%add2 = add nsw i32 %3, %s.0
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%add.ptr = getelementptr inbounds i32, i32* %x.addr.0, i32 4
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%sub = add i32 %n.addr.0, -4
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%sub3 = add nsw i32 %count.0, -1
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%cmp4 = icmp sgt i32 %count.0, 1
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br i1 %cmp4, label %do.body, label %if.end
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if.end: ; preds = %do.body, %entry
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%s.1 = phi i32 [ %m, %entry ], [ %add2, %do.body ]
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store i32 %s.1, i32* %z, align 4
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ret void
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}
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define void @nested(i32* nocapture readonly %x, i32* nocapture readnone %y, i32* nocapture %z, i32 %m, i32 %n) {
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; CHECK-LABEL: nested:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, lr}
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; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, lr}
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; CHECK-NEXT: cbz r3, .LBB1_8
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; CHECK-NEXT: @ %bb.1: @ %for.body.preheader
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; CHECK-NEXT: ldr r5, [sp, #28]
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; CHECK-NEXT: mov.w r12, #0
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; CHECK-NEXT: movs r1, #0
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; CHECK-NEXT: b .LBB1_4
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; CHECK-NEXT: .LBB1_2: @ in Loop: Header=BB1_4 Depth=1
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; CHECK-NEXT: mov r4, r3
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; CHECK-NEXT: .LBB1_3: @ %if.end
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; CHECK-NEXT: @ in Loop: Header=BB1_4 Depth=1
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; CHECK-NEXT: str.w r4, [r2, r1, lsl #2]
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; CHECK-NEXT: adds r1, #1
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; CHECK-NEXT: cmp r1, r3
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; CHECK-NEXT: beq .LBB1_8
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; CHECK-NEXT: .LBB1_4: @ %for.body
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; CHECK-NEXT: @ =>This Loop Header: Depth=1
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; CHECK-NEXT: @ Child Loop BB1_6 Depth 2
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; CHECK-NEXT: adds r7, r5, #3
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; CHECK-NEXT: cmp.w r12, r7, lsr #2
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; CHECK-NEXT: beq .LBB1_2
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; CHECK-NEXT: @ %bb.5: @ %do.body.preheader
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; CHECK-NEXT: @ in Loop: Header=BB1_4 Depth=1
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; CHECK-NEXT: bic r9, r7, #3
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; CHECK-NEXT: mov r7, r5
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; CHECK-NEXT: mov r4, r3
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; CHECK-NEXT: add.w r8, r0, r9, lsl #2
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; CHECK-NEXT: dlstp.32 lr, r5
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; CHECK-NEXT: .LBB1_6: @ %do.body
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; CHECK-NEXT: @ Parent Loop BB1_4 Depth=1
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; CHECK-NEXT: @ => This Inner Loop Header: Depth=2
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; CHECK-NEXT: vldrw.u32 q0, [r0], #16
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; CHECK-NEXT: vaddva.s32 r4, q0
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; CHECK-NEXT: letp lr, .LBB1_6
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; CHECK-NEXT: @ %bb.7: @ %if.end.loopexit
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; CHECK-NEXT: @ in Loop: Header=BB1_4 Depth=1
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; CHECK-NEXT: sub.w r5, r5, r9
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; CHECK-NEXT: mov r0, r8
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; CHECK-NEXT: b .LBB1_3
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; CHECK-NEXT: .LBB1_8: @ %for.cond.cleanup
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; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, pc}
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entry:
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%cmp20.not = icmp eq i32 %m, 0
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br i1 %cmp20.not, label %for.cond.cleanup, label %for.body
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for.cond.cleanup: ; preds = %if.end, %entry
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ret void
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for.body: ; preds = %entry, %if.end
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%x.addr.023 = phi i32* [ %x.addr.2, %if.end ], [ %x, %entry ]
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%a.022 = phi i32 [ %inc, %if.end ], [ 0, %entry ]
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%n.addr.021 = phi i32 [ %n.addr.2, %if.end ], [ %n, %entry ]
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%add = add i32 %n.addr.021, 3
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%div = lshr i32 %add, 2
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%cmp1.not = icmp eq i32 %div, 0
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br i1 %cmp1.not, label %if.end, label %do.body.preheader
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do.body.preheader: ; preds = %for.body
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%0 = and i32 %add, -4
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%scevgep = getelementptr i32, i32* %x.addr.023, i32 %0
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br label %do.body
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do.body: ; preds = %do.body.preheader, %do.body
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%n.addr.1 = phi i32 [ %sub, %do.body ], [ %n.addr.021, %do.body.preheader ]
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%count.0 = phi i32 [ %sub4, %do.body ], [ %div, %do.body.preheader ]
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%s.0 = phi i32 [ %add3, %do.body ], [ %m, %do.body.preheader ]
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%x.addr.1 = phi i32* [ %add.ptr, %do.body ], [ %x.addr.023, %do.body.preheader ]
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%1 = tail call <4 x i1> @llvm.arm.mve.vctp32(i32 %n.addr.1)
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%2 = bitcast i32* %x.addr.1 to <4 x i32>*
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%3 = load <4 x i32>, <4 x i32>* %2, align 4
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%4 = tail call i32 @llvm.arm.mve.addv.predicated.v4i32.v4i1(<4 x i32> %3, i32 0, <4 x i1> %1)
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%add3 = add nsw i32 %4, %s.0
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%add.ptr = getelementptr inbounds i32, i32* %x.addr.1, i32 4
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%sub = add i32 %n.addr.1, -4
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%sub4 = add nsw i32 %count.0, -1
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%cmp5 = icmp sgt i32 %count.0, 1
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br i1 %cmp5, label %do.body, label %if.end.loopexit
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if.end.loopexit: ; preds = %do.body
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%5 = sub i32 %n.addr.021, %0
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br label %if.end
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if.end: ; preds = %if.end.loopexit, %for.body
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%n.addr.2 = phi i32 [ %n.addr.021, %for.body ], [ %5, %if.end.loopexit ]
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%s.1 = phi i32 [ %m, %for.body ], [ %add3, %if.end.loopexit ]
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%x.addr.2 = phi i32* [ %x.addr.023, %for.body ], [ %scevgep, %if.end.loopexit ]
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%arrayidx = getelementptr inbounds i32, i32* %z, i32 %a.022
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store i32 %s.1, i32* %arrayidx, align 4
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%inc = add nuw nsw i32 %a.022, 1
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%exitcond.not = icmp eq i32 %inc, %m
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br i1 %exitcond.not, label %for.cond.cleanup, label %for.body
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}
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declare <4 x i1> @llvm.arm.mve.vctp32(i32)
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declare i32 @llvm.arm.mve.addv.predicated.v4i32.v4i1(<4 x i32>, i32, <4 x i1>)
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