Carl Ritson e5b0b434f6 [AMDGPU] Refactor MIMG tables to better handle hardware variants ...

Add mimgopc object to represent the opcode allowing different
opcodes for different hardware variants.
This enables image_atomic_fcmpswap, image_atomic_fmin, and
image_atomic_fmax on GFX10

Reviewed By: foad, rampitec

Differential Revision: https://reviews.llvm.org/D96309

2021-02-11 13:22:41 +09:00

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AArch64

[ARM] Update existing test case with +pauth targets

2021-01-11 15:39:13 +00:00

AMDGPU

[AMDGPU] Refactor MIMG tables to better handle hardware variants

2021-02-11 13:22:41 +09:00

ARC

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ARM

[ARM] Fix Asm/Disasm of TBB/TBH instructions

2020-07-22 09:31:56 +01:00

Hexagon

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Lanai

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Mips

[mips] Add tests to check disassembling of add.ps/mul.ps/sub.ps instructions

2020-11-13 14:31:12 +03:00

MSP430

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PowerPC

[PowerPC] Only use some extend mne if assembler is modern enough

2021-01-14 20:36:10 +00:00

RISCV

[RISCV] Add support for printing pcrel immediates as absolute addresses in llvm-objdump

2020-12-04 10:34:12 -08:00

Sparc

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SystemZ

[SystemZ] Support z15 processor name

2019-09-20 23:04:45 +00:00

WebAssembly

[WebAssembly] Remove exnref and br_on_exn

2021-01-09 02:02:54 -08:00

X86

[X86] Fix disassembly of x86-64 GDTLS code sequence

2021-02-02 11:35:00 +00:00

XCore

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