2f38a8fc57
For V_DOT2_F32_F16 and V_DOT2_F32_BF16 add their VOPDName and mark them with usesCustomInserter which will be used to add pre-RA register allocation hints to preferably assign dst and src2 to the same physical register. When the hint is satisfied, canMapVOP3PToVOPD recognises the instruction as eligible for VOPD pairing by checking if it is VOP2 like: dst==src2, no source modifiers, no clamp, and src1 is a register. Mark both instructions as commutable to allow a literal in src1 to be moved to src0, since VOPD only permits a literal in src0.
299 lines
11 KiB
C++
299 lines
11 KiB
C++
//===- GCNVOPDUtils.cpp - GCN VOPD Utils ------------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file This file contains the AMDGPU DAG scheduling
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/// mutation to pair VOPD instructions back to back. It also contains
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// subroutines useful in the creation of VOPD instructions
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//
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//===----------------------------------------------------------------------===//
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#include "GCNVOPDUtils.h"
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#include "AMDGPUSubtarget.h"
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#include "GCNSubtarget.h"
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#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
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#include "SIInstrInfo.h"
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#include "Utils/AMDGPUBaseInfo.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineOperand.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/MacroFusion.h"
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#include "llvm/CodeGen/ScheduleDAG.h"
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#include "llvm/CodeGen/ScheduleDAGMutation.h"
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#include "llvm/CodeGen/TargetInstrInfo.h"
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#include "llvm/MC/MCInst.h"
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using namespace llvm;
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#define DEBUG_TYPE "gcn-vopd-utils"
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// Check if MI is a VOP3P instruction with operands that satisfy the constraints
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// for mapping it to a VOP2/VOPD opcode: no modifiers, no clamp, src1 and src2
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// are registers (src0 can be register or literal), and src2 is same as dst.
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static bool canMapVOP3PToVOPD(const MachineInstr &MI) {
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unsigned Opc = MI.getOpcode();
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if (Opc != AMDGPU::V_DOT2_F32_F16 && Opc != AMDGPU::V_DOT2_F32_BF16)
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return false;
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// src0 can be register or literal
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int16_t Src0ModsIdx = getNamedOperandIdx(Opc, AMDGPU::OpName::src0_modifiers);
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if (MI.getOperand(Src0ModsIdx).getImm() != SISrcMods::OP_SEL_1)
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return false;
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int16_t Src1ModsIdx = getNamedOperandIdx(Opc, AMDGPU::OpName::src1_modifiers);
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if (MI.getOperand(Src1ModsIdx).getImm() != SISrcMods::OP_SEL_1)
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return false;
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int16_t Src1Idx = getNamedOperandIdx(Opc, AMDGPU::OpName::src1);
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if (!MI.getOperand(Src1Idx).isReg())
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return false;
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int16_t Src2ModsIdx = getNamedOperandIdx(Opc, AMDGPU::OpName::src2_modifiers);
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if (MI.getOperand(Src2ModsIdx).getImm() != SISrcMods::OP_SEL_1)
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return false;
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int16_t Src2Idx = getNamedOperandIdx(Opc, AMDGPU::OpName::src2);
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if (!MI.getOperand(Src2Idx).isReg())
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return false;
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int16_t ClampIdx = getNamedOperandIdx(Opc, AMDGPU::OpName::clamp);
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if (MI.getOperand(ClampIdx).getImm() != 0)
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return false;
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int16_t VdstIdx = getNamedOperandIdx(Opc, AMDGPU::OpName::vdst);
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return MI.getOperand(VdstIdx).getReg() == MI.getOperand(Src2Idx).getReg();
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}
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bool llvm::checkVOPDRegConstraints(const SIInstrInfo &TII,
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const MachineInstr &MIX,
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const MachineInstr &MIY, bool IsVOPD3) {
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namespace VOPD = AMDGPU::VOPD;
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const MachineFunction *MF = MIX.getMF();
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const GCNSubtarget &ST = MF->getSubtarget<GCNSubtarget>();
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if (IsVOPD3 && !ST.hasVOPD3())
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return false;
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if (!IsVOPD3 && ((TII.isVOP3(MIX) && !canMapVOP3PToVOPD(MIX)) ||
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(TII.isVOP3(MIY) && !canMapVOP3PToVOPD(MIY))))
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return false;
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if (TII.isDPP(MIX) || TII.isDPP(MIY))
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return false;
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const SIRegisterInfo *TRI = dyn_cast<SIRegisterInfo>(ST.getRegisterInfo());
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const MachineRegisterInfo &MRI = MF->getRegInfo();
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// Literals also count against scalar bus limit
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SmallVector<const MachineOperand *> UniqueLiterals;
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auto addLiteral = [&](const MachineOperand &Op) {
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for (auto &Literal : UniqueLiterals) {
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if (Literal->isIdenticalTo(Op))
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return;
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}
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UniqueLiterals.push_back(&Op);
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};
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SmallVector<Register> UniqueScalarRegs;
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// MIX must not modify any registers used by MIY.
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for (const auto &Use : MIY.uses())
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if (Use.isReg() && MIX.modifiesRegister(Use.getReg(), TRI))
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return false;
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auto getVRegIdx = [&](unsigned OpcodeIdx, unsigned OperandIdx) {
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const MachineInstr &MI = (OpcodeIdx == VOPD::X) ? MIX : MIY;
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const MachineOperand &Operand = MI.getOperand(OperandIdx);
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if (Operand.isReg() && TRI->isVectorRegister(MRI, Operand.getReg()))
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return Operand.getReg();
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return Register();
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};
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auto InstInfo = AMDGPU::getVOPDInstInfo(MIX.getDesc(), MIY.getDesc());
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for (auto CompIdx : VOPD::COMPONENTS) {
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const MachineInstr &MI = (CompIdx == VOPD::X) ? MIX : MIY;
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const MachineOperand &Src0 = *TII.getNamedOperand(MI, AMDGPU::OpName::src0);
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if (Src0.isReg()) {
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if (!TRI->isVectorRegister(MRI, Src0.getReg())) {
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if (!is_contained(UniqueScalarRegs, Src0.getReg()))
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UniqueScalarRegs.push_back(Src0.getReg());
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}
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} else if (!TII.isInlineConstant(Src0)) {
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if (IsVOPD3)
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return false;
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addLiteral(Src0);
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}
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if (InstInfo[CompIdx].hasMandatoryLiteral()) {
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if (IsVOPD3)
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return false;
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auto CompOprIdx = InstInfo[CompIdx].getMandatoryLiteralCompOperandIndex();
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addLiteral(MI.getOperand(CompOprIdx));
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}
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if (MI.getDesc().hasImplicitUseOfPhysReg(AMDGPU::VCC))
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UniqueScalarRegs.push_back(AMDGPU::VCC_LO);
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if (IsVOPD3) {
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for (auto OpName : {AMDGPU::OpName::src1, AMDGPU::OpName::src2}) {
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const MachineOperand *Src = TII.getNamedOperand(MI, OpName);
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if (!Src)
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continue;
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if (OpName == AMDGPU::OpName::src2) {
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if (AMDGPU::hasNamedOperand(MI.getOpcode(), AMDGPU::OpName::bitop3))
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continue;
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if (MI.getOpcode() == AMDGPU::V_CNDMASK_B32_e64) {
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UniqueScalarRegs.push_back(Src->getReg());
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continue;
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}
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}
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if (!Src->isReg() || !TRI->isVGPR(MRI, Src->getReg()))
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return false;
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}
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for (auto OpName : {AMDGPU::OpName::clamp, AMDGPU::OpName::omod,
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AMDGPU::OpName::op_sel}) {
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if (TII.hasModifiersSet(MI, OpName))
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return false;
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}
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// Neg is allowed, other modifiers are not. NB: even though sext has the
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// same value as neg, there are no combinable instructions with sext.
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for (auto OpName :
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{AMDGPU::OpName::src0_modifiers, AMDGPU::OpName::src1_modifiers,
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AMDGPU::OpName::src2_modifiers}) {
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const MachineOperand *Mods = TII.getNamedOperand(MI, OpName);
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if (Mods && (Mods->getImm() & ~SISrcMods::NEG))
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return false;
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}
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}
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}
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if (UniqueLiterals.size() > 1)
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return false;
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if ((UniqueLiterals.size() + UniqueScalarRegs.size()) > 2)
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return false;
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// On GFX1170+ if both OpX and OpY are V_MOV_B32 then OPY uses SRC2
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// source-cache.
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bool SkipSrc = (ST.hasGFX11_7Insts() || ST.hasGFX12Insts()) &&
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MIX.getOpcode() == AMDGPU::V_MOV_B32_e32 &&
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MIY.getOpcode() == AMDGPU::V_MOV_B32_e32;
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bool AllowSameVGPR = ST.hasGFX1250Insts();
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if (InstInfo.hasInvalidOperand(getVRegIdx, *TRI, SkipSrc, AllowSameVGPR,
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IsVOPD3))
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return false;
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if (IsVOPD3) {
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// BITOP3 can be converted to DUAL_BITOP2 only if src2 is zero.
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// MIX check is only relevant to scheduling?
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if (AMDGPU::hasNamedOperand(MIX.getOpcode(), AMDGPU::OpName::bitop3)) {
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const MachineOperand &Src2 =
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*TII.getNamedOperand(MIX, AMDGPU::OpName::src2);
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if (!Src2.isImm() || Src2.getImm())
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return false;
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}
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if (AMDGPU::hasNamedOperand(MIY.getOpcode(), AMDGPU::OpName::bitop3)) {
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const MachineOperand &Src2 =
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*TII.getNamedOperand(MIY, AMDGPU::OpName::src2);
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if (!Src2.isImm() || Src2.getImm())
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return false;
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}
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}
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LLVM_DEBUG(dbgs() << "VOPD Reg Constraints Passed\n\tX: " << MIX
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<< "\n\tY: " << MIY << "\n");
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return true;
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}
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/// Check if the instr pair, FirstMI and SecondMI, should be scheduled
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/// together. Given SecondMI, when FirstMI is unspecified, then check if
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/// SecondMI may be part of a fused pair at all.
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static bool shouldScheduleVOPDAdjacent(const TargetInstrInfo &TII,
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const TargetSubtargetInfo &TSI,
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const MachineInstr *FirstMI,
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const MachineInstr &SecondMI) {
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const SIInstrInfo &STII = static_cast<const SIInstrInfo &>(TII);
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const GCNSubtarget &ST = STII.getSubtarget();
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unsigned EncodingFamily = AMDGPU::getVOPDEncodingFamily(ST);
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unsigned Opc2 = SecondMI.getOpcode();
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const auto checkVOPD = [&](bool VOPD3) -> bool {
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auto SecondCanBeVOPD = AMDGPU::getCanBeVOPD(Opc2, EncodingFamily, VOPD3);
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// One instruction case
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if (!FirstMI)
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return SecondCanBeVOPD.Y || SecondCanBeVOPD.X;
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unsigned Opc = FirstMI->getOpcode();
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auto FirstCanBeVOPD = AMDGPU::getCanBeVOPD(Opc, EncodingFamily, VOPD3);
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if (!((FirstCanBeVOPD.X && SecondCanBeVOPD.Y) ||
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(FirstCanBeVOPD.Y && SecondCanBeVOPD.X)))
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return false;
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#ifdef EXPENSIVE_CHECKS
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assert([&]() -> bool {
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for (auto MII = MachineBasicBlock::const_iterator(FirstMI);
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MII != FirstMI->getParent()->instr_end(); ++MII) {
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if (&*MII == &SecondMI)
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return true;
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}
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return false;
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}() && "Expected FirstMI to precede SecondMI");
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#endif
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return checkVOPDRegConstraints(STII, *FirstMI, SecondMI, VOPD3);
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};
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return checkVOPD(false) || (ST.hasVOPD3() && checkVOPD(true));
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}
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namespace {
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/// Adapts design from MacroFusion
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/// Puts valid candidate instructions back-to-back so they can easily
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/// be turned into VOPD instructions
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/// Greedily pairs instruction candidates. O(n^2) algorithm.
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struct VOPDPairingMutation : ScheduleDAGMutation {
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MacroFusionPredTy shouldScheduleAdjacent; // NOLINT: function pointer
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VOPDPairingMutation(
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MacroFusionPredTy shouldScheduleAdjacent) // NOLINT: function pointer
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: shouldScheduleAdjacent(shouldScheduleAdjacent) {}
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void apply(ScheduleDAGInstrs *DAG) override {
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const TargetInstrInfo &TII = *DAG->TII;
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const GCNSubtarget &ST = DAG->MF.getSubtarget<GCNSubtarget>();
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if (!AMDGPU::hasVOPD(ST) || !ST.isWave32()) {
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LLVM_DEBUG(dbgs() << "Target does not support VOPDPairingMutation\n");
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return;
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}
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std::vector<SUnit>::iterator ISUI, JSUI;
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for (ISUI = DAG->SUnits.begin(); ISUI != DAG->SUnits.end(); ++ISUI) {
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const MachineInstr *IMI = ISUI->getInstr();
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if (!shouldScheduleAdjacent(TII, ST, nullptr, *IMI))
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continue;
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if (!hasLessThanNumFused(*ISUI, 2))
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continue;
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for (JSUI = ISUI + 1; JSUI != DAG->SUnits.end(); ++JSUI) {
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if (JSUI->isBoundaryNode())
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continue;
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const MachineInstr *JMI = JSUI->getInstr();
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if (!hasLessThanNumFused(*JSUI, 2) ||
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!shouldScheduleAdjacent(TII, ST, IMI, *JMI))
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continue;
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if (fuseInstructionPair(*DAG, *ISUI, *JSUI))
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break;
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}
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}
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LLVM_DEBUG(dbgs() << "Completed VOPDPairingMutation\n");
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}
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};
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} // namespace
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std::unique_ptr<ScheduleDAGMutation> llvm::createVOPDPairingMutation() {
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return std::make_unique<VOPDPairingMutation>(shouldScheduleVOPDAdjacent);
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}
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