93b90a532d
MBBFrameObjsReachingDefs was not being built correctly since we were not inserting into a reference of Frame2InstrIdx. If there was multiple stack slot defs in the same basic block, then the bug would occur. This PR fixes this problem while simplifying the insertion logic. Additionally, when lookup into MBBFrameObjsReachingDefs was occurring, there was a chance that there was no entry in the map, in the case that there was no reaching def. This was causing us to return a default value, which may or may not have been correct. This patch returns the correct value now.
802 lines
26 KiB
C++
802 lines
26 KiB
C++
//===---- ReachingDefAnalysis.cpp - Reaching Def Analysis ---*- C++ -*-----===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/CodeGen/ReachingDefAnalysis.h"
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#include "llvm/ADT/SetOperations.h"
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#include "llvm/ADT/SmallSet.h"
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#include "llvm/CodeGen/LiveRegUnits.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/TargetInstrInfo.h"
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#include "llvm/CodeGen/TargetRegisterInfo.h"
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#include "llvm/CodeGen/TargetSubtargetInfo.h"
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#include "llvm/Support/Debug.h"
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using namespace llvm;
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#define DEBUG_TYPE "reaching-defs-analysis"
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static cl::opt<bool> PrintAllReachingDefs("print-all-reaching-defs", cl::Hidden,
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cl::desc("Used for test purpuses"),
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cl::Hidden);
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char ReachingDefAnalysis::ID = 0;
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INITIALIZE_PASS(ReachingDefAnalysis, DEBUG_TYPE, "ReachingDefAnalysis", false,
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true)
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static bool isValidReg(const MachineOperand &MO) {
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return MO.isReg() && MO.getReg();
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}
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static bool isValidRegUse(const MachineOperand &MO) {
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return isValidReg(MO) && MO.isUse();
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}
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static bool isValidRegUseOf(const MachineOperand &MO, Register Reg,
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const TargetRegisterInfo *TRI) {
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if (!isValidRegUse(MO))
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return false;
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return TRI->regsOverlap(MO.getReg(), Reg);
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}
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static bool isValidRegDef(const MachineOperand &MO) {
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return isValidReg(MO) && MO.isDef();
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}
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static bool isValidRegDefOf(const MachineOperand &MO, Register Reg,
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const TargetRegisterInfo *TRI) {
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if (!isValidRegDef(MO))
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return false;
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return TRI->regsOverlap(MO.getReg(), Reg);
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}
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static bool isFIDef(const MachineInstr &MI, int FrameIndex,
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const TargetInstrInfo *TII) {
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int DefFrameIndex = 0;
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int SrcFrameIndex = 0;
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if (TII->isStoreToStackSlot(MI, DefFrameIndex) ||
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TII->isStackSlotCopy(MI, DefFrameIndex, SrcFrameIndex))
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return DefFrameIndex == FrameIndex;
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return false;
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}
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void ReachingDefAnalysis::enterBasicBlock(MachineBasicBlock *MBB) {
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unsigned MBBNumber = MBB->getNumber();
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assert(MBBNumber < MBBReachingDefs.numBlockIDs() &&
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"Unexpected basic block number.");
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MBBReachingDefs.startBasicBlock(MBBNumber, NumRegUnits);
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// Reset instruction counter in each basic block.
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CurInstr = 0;
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// Set up LiveRegs to represent registers entering MBB.
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// Default values are 'nothing happened a long time ago'.
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if (LiveRegs.empty())
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LiveRegs.assign(NumRegUnits, ReachingDefDefaultVal);
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// This is the entry block.
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if (MBB->pred_empty()) {
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for (const auto &LI : MBB->liveins()) {
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for (MCRegUnit Unit : TRI->regunits(LI.PhysReg)) {
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// Treat function live-ins as if they were defined just before the first
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// instruction. Usually, function arguments are set up immediately
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// before the call.
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if (LiveRegs[Unit] != -1) {
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LiveRegs[Unit] = -1;
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MBBReachingDefs.append(MBBNumber, Unit, -1);
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}
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}
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}
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LLVM_DEBUG(dbgs() << printMBBReference(*MBB) << ": entry\n");
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return;
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}
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// Try to coalesce live-out registers from predecessors.
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for (MachineBasicBlock *pred : MBB->predecessors()) {
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assert(unsigned(pred->getNumber()) < MBBOutRegsInfos.size() &&
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"Should have pre-allocated MBBInfos for all MBBs");
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const LiveRegsDefInfo &Incoming = MBBOutRegsInfos[pred->getNumber()];
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// Incoming is null if this is a backedge from a BB
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// we haven't processed yet
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if (Incoming.empty())
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continue;
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// Find the most recent reaching definition from a predecessor.
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for (unsigned Unit = 0; Unit != NumRegUnits; ++Unit)
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LiveRegs[Unit] = std::max(LiveRegs[Unit], Incoming[Unit]);
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}
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// Insert the most recent reaching definition we found.
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for (unsigned Unit = 0; Unit != NumRegUnits; ++Unit)
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if (LiveRegs[Unit] != ReachingDefDefaultVal)
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MBBReachingDefs.append(MBBNumber, Unit, LiveRegs[Unit]);
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}
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void ReachingDefAnalysis::leaveBasicBlock(MachineBasicBlock *MBB) {
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assert(!LiveRegs.empty() && "Must enter basic block first.");
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unsigned MBBNumber = MBB->getNumber();
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assert(MBBNumber < MBBOutRegsInfos.size() &&
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"Unexpected basic block number.");
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// Save register clearances at end of MBB - used by enterBasicBlock().
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MBBOutRegsInfos[MBBNumber] = LiveRegs;
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// While processing the basic block, we kept `Def` relative to the start
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// of the basic block for convenience. However, future use of this information
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// only cares about the clearance from the end of the block, so adjust
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// everything to be relative to the end of the basic block.
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for (int &OutLiveReg : MBBOutRegsInfos[MBBNumber])
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if (OutLiveReg != ReachingDefDefaultVal)
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OutLiveReg -= CurInstr;
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LiveRegs.clear();
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}
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void ReachingDefAnalysis::processDefs(MachineInstr *MI) {
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assert(!MI->isDebugInstr() && "Won't process debug instructions");
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unsigned MBBNumber = MI->getParent()->getNumber();
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assert(MBBNumber < MBBReachingDefs.numBlockIDs() &&
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"Unexpected basic block number.");
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for (auto &MO : MI->operands()) {
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if (MO.isFI()) {
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int FrameIndex = MO.getIndex();
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assert(FrameIndex >= 0 && "Can't handle negative frame indicies yet!");
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if (!isFIDef(*MI, FrameIndex, TII))
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continue;
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MBBFrameObjsReachingDefs[{MBBNumber, FrameIndex}].push_back(CurInstr);
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}
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if (!isValidRegDef(MO))
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continue;
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for (MCRegUnit Unit : TRI->regunits(MO.getReg().asMCReg())) {
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// This instruction explicitly defines the current reg unit.
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LLVM_DEBUG(dbgs() << printRegUnit(Unit, TRI) << ":\t" << CurInstr << '\t'
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<< *MI);
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// How many instructions since this reg unit was last written?
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if (LiveRegs[Unit] != CurInstr) {
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LiveRegs[Unit] = CurInstr;
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MBBReachingDefs.append(MBBNumber, Unit, CurInstr);
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}
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}
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}
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InstIds[MI] = CurInstr;
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++CurInstr;
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}
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void ReachingDefAnalysis::reprocessBasicBlock(MachineBasicBlock *MBB) {
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unsigned MBBNumber = MBB->getNumber();
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assert(MBBNumber < MBBReachingDefs.numBlockIDs() &&
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"Unexpected basic block number.");
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// Count number of non-debug instructions for end of block adjustment.
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auto NonDbgInsts =
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instructionsWithoutDebug(MBB->instr_begin(), MBB->instr_end());
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int NumInsts = std::distance(NonDbgInsts.begin(), NonDbgInsts.end());
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// When reprocessing a block, the only thing we need to do is check whether
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// there is now a more recent incoming reaching definition from a predecessor.
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for (MachineBasicBlock *pred : MBB->predecessors()) {
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assert(unsigned(pred->getNumber()) < MBBOutRegsInfos.size() &&
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"Should have pre-allocated MBBInfos for all MBBs");
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const LiveRegsDefInfo &Incoming = MBBOutRegsInfos[pred->getNumber()];
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// Incoming may be empty for dead predecessors.
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if (Incoming.empty())
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continue;
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for (unsigned Unit = 0; Unit != NumRegUnits; ++Unit) {
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int Def = Incoming[Unit];
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if (Def == ReachingDefDefaultVal)
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continue;
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auto Defs = MBBReachingDefs.defs(MBBNumber, Unit);
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if (!Defs.empty() && Defs.front() < 0) {
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if (Defs.front() >= Def)
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continue;
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// Update existing reaching def from predecessor to a more recent one.
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MBBReachingDefs.replaceFront(MBBNumber, Unit, Def);
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} else {
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// Insert new reaching def from predecessor.
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MBBReachingDefs.prepend(MBBNumber, Unit, Def);
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}
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// Update reaching def at end of BB. Keep in mind that these are
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// adjusted relative to the end of the basic block.
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if (MBBOutRegsInfos[MBBNumber][Unit] < Def - NumInsts)
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MBBOutRegsInfos[MBBNumber][Unit] = Def - NumInsts;
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}
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}
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}
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void ReachingDefAnalysis::processBasicBlock(
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const LoopTraversal::TraversedMBBInfo &TraversedMBB) {
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MachineBasicBlock *MBB = TraversedMBB.MBB;
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LLVM_DEBUG(dbgs() << printMBBReference(*MBB)
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<< (!TraversedMBB.IsDone ? ": incomplete\n"
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: ": all preds known\n"));
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if (!TraversedMBB.PrimaryPass) {
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// Reprocess MBB that is part of a loop.
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reprocessBasicBlock(MBB);
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return;
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}
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enterBasicBlock(MBB);
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for (MachineInstr &MI :
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instructionsWithoutDebug(MBB->instr_begin(), MBB->instr_end()))
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processDefs(&MI);
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leaveBasicBlock(MBB);
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}
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void ReachingDefAnalysis::printAllReachingDefs(MachineFunction &MF) {
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dbgs() << "RDA results for " << MF.getName() << "\n";
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int Num = 0;
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DenseMap<MachineInstr *, int> InstToNumMap;
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SmallPtrSet<MachineInstr *, 2> Defs;
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for (MachineBasicBlock &MBB : MF) {
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for (MachineInstr &MI : MBB) {
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for (MachineOperand &MO : MI.operands()) {
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Register Reg;
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if (MO.isFI()) {
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int FrameIndex = MO.getIndex();
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assert(FrameIndex >= 0 &&
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"Can't handle negative frame indicies yet!");
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Reg = Register::index2StackSlot(FrameIndex);
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} else if (MO.isReg()) {
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if (MO.isDef())
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continue;
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Reg = MO.getReg();
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if (!Reg.isValid())
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continue;
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} else
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continue;
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Defs.clear();
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getGlobalReachingDefs(&MI, Reg, Defs);
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MO.print(dbgs(), TRI);
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SmallVector<int, 0> Nums;
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for (MachineInstr *Def : Defs)
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Nums.push_back(InstToNumMap[Def]);
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llvm::sort(Nums);
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dbgs() << ":{ ";
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for (int Num : Nums)
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dbgs() << Num << " ";
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dbgs() << "}\n";
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}
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dbgs() << Num << ": " << MI << "\n";
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InstToNumMap[&MI] = Num;
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++Num;
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}
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}
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}
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bool ReachingDefAnalysis::runOnMachineFunction(MachineFunction &mf) {
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MF = &mf;
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TRI = MF->getSubtarget().getRegisterInfo();
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const TargetSubtargetInfo &STI = MF->getSubtarget();
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TRI = STI.getRegisterInfo();
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TII = STI.getInstrInfo();
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LLVM_DEBUG(dbgs() << "********** REACHING DEFINITION ANALYSIS **********\n");
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init();
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traverse();
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if (PrintAllReachingDefs)
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printAllReachingDefs(*MF);
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return false;
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}
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void ReachingDefAnalysis::releaseMemory() {
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// Clear the internal vectors.
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MBBOutRegsInfos.clear();
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MBBReachingDefs.clear();
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MBBFrameObjsReachingDefs.clear();
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InstIds.clear();
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LiveRegs.clear();
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}
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void ReachingDefAnalysis::reset() {
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releaseMemory();
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init();
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traverse();
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}
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void ReachingDefAnalysis::init() {
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NumRegUnits = TRI->getNumRegUnits();
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NumStackObjects = MF->getFrameInfo().getNumObjects();
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ObjectIndexBegin = MF->getFrameInfo().getObjectIndexBegin();
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MBBReachingDefs.init(MF->getNumBlockIDs());
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// Initialize the MBBOutRegsInfos
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MBBOutRegsInfos.resize(MF->getNumBlockIDs());
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LoopTraversal Traversal;
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TraversedMBBOrder = Traversal.traverse(*MF);
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}
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void ReachingDefAnalysis::traverse() {
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// Traverse the basic blocks.
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for (LoopTraversal::TraversedMBBInfo TraversedMBB : TraversedMBBOrder)
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processBasicBlock(TraversedMBB);
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#ifndef NDEBUG
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// Make sure reaching defs are sorted and unique.
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for (unsigned MBBNumber = 0, NumBlockIDs = MF->getNumBlockIDs();
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MBBNumber != NumBlockIDs; ++MBBNumber) {
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for (unsigned Unit = 0; Unit != NumRegUnits; ++Unit) {
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int LastDef = ReachingDefDefaultVal;
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for (int Def : MBBReachingDefs.defs(MBBNumber, Unit)) {
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assert(Def > LastDef && "Defs must be sorted and unique");
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LastDef = Def;
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}
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}
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}
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#endif
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}
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int ReachingDefAnalysis::getReachingDef(MachineInstr *MI, Register Reg) const {
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assert(InstIds.count(MI) && "Unexpected machine instuction.");
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int InstId = InstIds.lookup(MI);
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int DefRes = ReachingDefDefaultVal;
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unsigned MBBNumber = MI->getParent()->getNumber();
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assert(MBBNumber < MBBReachingDefs.numBlockIDs() &&
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"Unexpected basic block number.");
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int LatestDef = ReachingDefDefaultVal;
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if (Reg.isStack()) {
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// Check that there was a reaching def.
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int FrameIndex = Reg.stackSlotIndex();
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auto Lookup = MBBFrameObjsReachingDefs.find({MBBNumber, FrameIndex});
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if (Lookup == MBBFrameObjsReachingDefs.end())
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return LatestDef;
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auto &Defs = Lookup->second;
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for (int Def : Defs) {
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if (Def >= InstId)
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break;
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DefRes = Def;
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}
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LatestDef = std::max(LatestDef, DefRes);
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return LatestDef;
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}
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for (MCRegUnit Unit : TRI->regunits(Reg)) {
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for (int Def : MBBReachingDefs.defs(MBBNumber, Unit)) {
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if (Def >= InstId)
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break;
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DefRes = Def;
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}
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LatestDef = std::max(LatestDef, DefRes);
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}
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return LatestDef;
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}
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MachineInstr *ReachingDefAnalysis::getReachingLocalMIDef(MachineInstr *MI,
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Register Reg) const {
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return hasLocalDefBefore(MI, Reg)
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? getInstFromId(MI->getParent(), getReachingDef(MI, Reg))
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: nullptr;
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}
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bool ReachingDefAnalysis::hasSameReachingDef(MachineInstr *A, MachineInstr *B,
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Register Reg) const {
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MachineBasicBlock *ParentA = A->getParent();
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MachineBasicBlock *ParentB = B->getParent();
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if (ParentA != ParentB)
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return false;
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return getReachingDef(A, Reg) == getReachingDef(B, Reg);
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}
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MachineInstr *ReachingDefAnalysis::getInstFromId(MachineBasicBlock *MBB,
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int InstId) const {
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assert(static_cast<size_t>(MBB->getNumber()) <
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MBBReachingDefs.numBlockIDs() &&
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"Unexpected basic block number.");
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assert(InstId < static_cast<int>(MBB->size()) &&
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"Unexpected instruction id.");
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if (InstId < 0)
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return nullptr;
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for (auto &MI : *MBB) {
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auto F = InstIds.find(&MI);
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if (F != InstIds.end() && F->second == InstId)
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return &MI;
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}
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return nullptr;
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}
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int ReachingDefAnalysis::getClearance(MachineInstr *MI, Register Reg) const {
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assert(InstIds.count(MI) && "Unexpected machine instuction.");
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return InstIds.lookup(MI) - getReachingDef(MI, Reg);
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}
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bool ReachingDefAnalysis::hasLocalDefBefore(MachineInstr *MI,
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Register Reg) const {
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return getReachingDef(MI, Reg) >= 0;
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}
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void ReachingDefAnalysis::getReachingLocalUses(MachineInstr *Def, Register Reg,
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InstSet &Uses) const {
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MachineBasicBlock *MBB = Def->getParent();
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MachineBasicBlock::iterator MI = MachineBasicBlock::iterator(Def);
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while (++MI != MBB->end()) {
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if (MI->isDebugInstr())
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continue;
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// If/when we find a new reaching def, we know that there's no more uses
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// of 'Def'.
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if (getReachingLocalMIDef(&*MI, Reg) != Def)
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return;
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for (auto &MO : MI->operands()) {
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if (!isValidRegUseOf(MO, Reg, TRI))
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continue;
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Uses.insert(&*MI);
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if (MO.isKill())
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return;
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}
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}
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}
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bool ReachingDefAnalysis::getLiveInUses(MachineBasicBlock *MBB, Register Reg,
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InstSet &Uses) const {
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for (MachineInstr &MI :
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instructionsWithoutDebug(MBB->instr_begin(), MBB->instr_end())) {
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for (auto &MO : MI.operands()) {
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if (!isValidRegUseOf(MO, Reg, TRI))
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continue;
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if (getReachingDef(&MI, Reg) >= 0)
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return false;
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Uses.insert(&MI);
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}
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}
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auto Last = MBB->getLastNonDebugInstr();
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if (Last == MBB->end())
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return true;
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return isReachingDefLiveOut(&*Last, Reg);
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}
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void ReachingDefAnalysis::getGlobalUses(MachineInstr *MI, Register Reg,
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InstSet &Uses) const {
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MachineBasicBlock *MBB = MI->getParent();
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// Collect the uses that each def touches within the block.
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getReachingLocalUses(MI, Reg, Uses);
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// Handle live-out values.
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if (auto *LiveOut = getLocalLiveOutMIDef(MI->getParent(), Reg)) {
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if (LiveOut != MI)
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return;
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SmallVector<MachineBasicBlock *, 4> ToVisit(MBB->successors());
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SmallPtrSet<MachineBasicBlock*, 4>Visited;
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while (!ToVisit.empty()) {
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MachineBasicBlock *MBB = ToVisit.pop_back_val();
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if (Visited.count(MBB) || !MBB->isLiveIn(Reg))
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continue;
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if (getLiveInUses(MBB, Reg, Uses))
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llvm::append_range(ToVisit, MBB->successors());
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Visited.insert(MBB);
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}
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}
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|
}
|
|
|
|
void ReachingDefAnalysis::getGlobalReachingDefs(MachineInstr *MI, Register Reg,
|
|
InstSet &Defs) const {
|
|
if (auto *Def = getUniqueReachingMIDef(MI, Reg)) {
|
|
Defs.insert(Def);
|
|
return;
|
|
}
|
|
|
|
for (auto *MBB : MI->getParent()->predecessors())
|
|
getLiveOuts(MBB, Reg, Defs);
|
|
}
|
|
|
|
void ReachingDefAnalysis::getLiveOuts(MachineBasicBlock *MBB, Register Reg,
|
|
InstSet &Defs) const {
|
|
SmallPtrSet<MachineBasicBlock*, 2> VisitedBBs;
|
|
getLiveOuts(MBB, Reg, Defs, VisitedBBs);
|
|
}
|
|
|
|
void ReachingDefAnalysis::getLiveOuts(MachineBasicBlock *MBB, Register Reg,
|
|
InstSet &Defs,
|
|
BlockSet &VisitedBBs) const {
|
|
if (VisitedBBs.count(MBB))
|
|
return;
|
|
|
|
VisitedBBs.insert(MBB);
|
|
LiveRegUnits LiveRegs(*TRI);
|
|
LiveRegs.addLiveOuts(*MBB);
|
|
if (Reg.isPhysical() && LiveRegs.available(Reg))
|
|
return;
|
|
|
|
if (auto *Def = getLocalLiveOutMIDef(MBB, Reg))
|
|
Defs.insert(Def);
|
|
else
|
|
for (auto *Pred : MBB->predecessors())
|
|
getLiveOuts(Pred, Reg, Defs, VisitedBBs);
|
|
}
|
|
|
|
MachineInstr *ReachingDefAnalysis::getUniqueReachingMIDef(MachineInstr *MI,
|
|
Register Reg) const {
|
|
// If there's a local def before MI, return it.
|
|
MachineInstr *LocalDef = getReachingLocalMIDef(MI, Reg);
|
|
if (LocalDef && InstIds.lookup(LocalDef) < InstIds.lookup(MI))
|
|
return LocalDef;
|
|
|
|
SmallPtrSet<MachineInstr*, 2> Incoming;
|
|
MachineBasicBlock *Parent = MI->getParent();
|
|
for (auto *Pred : Parent->predecessors())
|
|
getLiveOuts(Pred, Reg, Incoming);
|
|
|
|
// Check that we have a single incoming value and that it does not
|
|
// come from the same block as MI - since it would mean that the def
|
|
// is executed after MI.
|
|
if (Incoming.size() == 1 && (*Incoming.begin())->getParent() != Parent)
|
|
return *Incoming.begin();
|
|
return nullptr;
|
|
}
|
|
|
|
MachineInstr *ReachingDefAnalysis::getMIOperand(MachineInstr *MI,
|
|
unsigned Idx) const {
|
|
assert(MI->getOperand(Idx).isReg() && "Expected register operand");
|
|
return getUniqueReachingMIDef(MI, MI->getOperand(Idx).getReg());
|
|
}
|
|
|
|
MachineInstr *ReachingDefAnalysis::getMIOperand(MachineInstr *MI,
|
|
MachineOperand &MO) const {
|
|
assert(MO.isReg() && "Expected register operand");
|
|
return getUniqueReachingMIDef(MI, MO.getReg());
|
|
}
|
|
|
|
bool ReachingDefAnalysis::isRegUsedAfter(MachineInstr *MI, Register Reg) const {
|
|
MachineBasicBlock *MBB = MI->getParent();
|
|
LiveRegUnits LiveRegs(*TRI);
|
|
LiveRegs.addLiveOuts(*MBB);
|
|
|
|
// Yes if the register is live out of the basic block.
|
|
if (!LiveRegs.available(Reg))
|
|
return true;
|
|
|
|
// Walk backwards through the block to see if the register is live at some
|
|
// point.
|
|
for (MachineInstr &Last :
|
|
instructionsWithoutDebug(MBB->instr_rbegin(), MBB->instr_rend())) {
|
|
LiveRegs.stepBackward(Last);
|
|
if (!LiveRegs.available(Reg))
|
|
return InstIds.lookup(&Last) > InstIds.lookup(MI);
|
|
}
|
|
return false;
|
|
}
|
|
|
|
bool ReachingDefAnalysis::isRegDefinedAfter(MachineInstr *MI,
|
|
Register Reg) const {
|
|
MachineBasicBlock *MBB = MI->getParent();
|
|
auto Last = MBB->getLastNonDebugInstr();
|
|
if (Last != MBB->end() &&
|
|
getReachingDef(MI, Reg) != getReachingDef(&*Last, Reg))
|
|
return true;
|
|
|
|
if (auto *Def = getLocalLiveOutMIDef(MBB, Reg))
|
|
return Def == getReachingLocalMIDef(MI, Reg);
|
|
|
|
return false;
|
|
}
|
|
|
|
bool ReachingDefAnalysis::isReachingDefLiveOut(MachineInstr *MI,
|
|
Register Reg) const {
|
|
MachineBasicBlock *MBB = MI->getParent();
|
|
LiveRegUnits LiveRegs(*TRI);
|
|
LiveRegs.addLiveOuts(*MBB);
|
|
if (Reg.isPhysical() && LiveRegs.available(Reg))
|
|
return false;
|
|
|
|
auto Last = MBB->getLastNonDebugInstr();
|
|
int Def = getReachingDef(MI, Reg);
|
|
if (Last != MBB->end() && getReachingDef(&*Last, Reg) != Def)
|
|
return false;
|
|
|
|
// Finally check that the last instruction doesn't redefine the register.
|
|
for (auto &MO : Last->operands())
|
|
if (isValidRegDefOf(MO, Reg, TRI))
|
|
return false;
|
|
|
|
return true;
|
|
}
|
|
|
|
MachineInstr *ReachingDefAnalysis::getLocalLiveOutMIDef(MachineBasicBlock *MBB,
|
|
Register Reg) const {
|
|
LiveRegUnits LiveRegs(*TRI);
|
|
LiveRegs.addLiveOuts(*MBB);
|
|
if (Reg.isPhysical() && LiveRegs.available(Reg))
|
|
return nullptr;
|
|
|
|
auto Last = MBB->getLastNonDebugInstr();
|
|
if (Last == MBB->end())
|
|
return nullptr;
|
|
|
|
if (Reg.isStack()) {
|
|
int FrameIndex = Reg.stackSlotIndex();
|
|
if (isFIDef(*Last, FrameIndex, TII))
|
|
return &*Last;
|
|
}
|
|
|
|
int Def = getReachingDef(&*Last, Reg);
|
|
|
|
for (auto &MO : Last->operands())
|
|
if (isValidRegDefOf(MO, Reg, TRI))
|
|
return &*Last;
|
|
|
|
return Def < 0 ? nullptr : getInstFromId(MBB, Def);
|
|
}
|
|
|
|
static bool mayHaveSideEffects(MachineInstr &MI) {
|
|
return MI.mayLoadOrStore() || MI.mayRaiseFPException() ||
|
|
MI.hasUnmodeledSideEffects() || MI.isTerminator() ||
|
|
MI.isCall() || MI.isBarrier() || MI.isBranch() || MI.isReturn();
|
|
}
|
|
|
|
// Can we safely move 'From' to just before 'To'? To satisfy this, 'From' must
|
|
// not define a register that is used by any instructions, after and including,
|
|
// 'To'. These instructions also must not redefine any of Froms operands.
|
|
template<typename Iterator>
|
|
bool ReachingDefAnalysis::isSafeToMove(MachineInstr *From,
|
|
MachineInstr *To) const {
|
|
if (From->getParent() != To->getParent() || From == To)
|
|
return false;
|
|
|
|
SmallSet<int, 2> Defs;
|
|
// First check that From would compute the same value if moved.
|
|
for (auto &MO : From->operands()) {
|
|
if (!isValidReg(MO))
|
|
continue;
|
|
if (MO.isDef())
|
|
Defs.insert(MO.getReg());
|
|
else if (!hasSameReachingDef(From, To, MO.getReg()))
|
|
return false;
|
|
}
|
|
|
|
// Now walk checking that the rest of the instructions will compute the same
|
|
// value and that we're not overwriting anything. Don't move the instruction
|
|
// past any memory, control-flow or other ambiguous instructions.
|
|
for (auto I = ++Iterator(From), E = Iterator(To); I != E; ++I) {
|
|
if (mayHaveSideEffects(*I))
|
|
return false;
|
|
for (auto &MO : I->operands())
|
|
if (MO.isReg() && MO.getReg() && Defs.count(MO.getReg()))
|
|
return false;
|
|
}
|
|
return true;
|
|
}
|
|
|
|
bool ReachingDefAnalysis::isSafeToMoveForwards(MachineInstr *From,
|
|
MachineInstr *To) const {
|
|
using Iterator = MachineBasicBlock::iterator;
|
|
// Walk forwards until we find the instruction.
|
|
for (auto I = Iterator(From), E = From->getParent()->end(); I != E; ++I)
|
|
if (&*I == To)
|
|
return isSafeToMove<Iterator>(From, To);
|
|
return false;
|
|
}
|
|
|
|
bool ReachingDefAnalysis::isSafeToMoveBackwards(MachineInstr *From,
|
|
MachineInstr *To) const {
|
|
using Iterator = MachineBasicBlock::reverse_iterator;
|
|
// Walk backwards until we find the instruction.
|
|
for (auto I = Iterator(From), E = From->getParent()->rend(); I != E; ++I)
|
|
if (&*I == To)
|
|
return isSafeToMove<Iterator>(From, To);
|
|
return false;
|
|
}
|
|
|
|
bool ReachingDefAnalysis::isSafeToRemove(MachineInstr *MI,
|
|
InstSet &ToRemove) const {
|
|
SmallPtrSet<MachineInstr*, 1> Ignore;
|
|
SmallPtrSet<MachineInstr*, 2> Visited;
|
|
return isSafeToRemove(MI, Visited, ToRemove, Ignore);
|
|
}
|
|
|
|
bool
|
|
ReachingDefAnalysis::isSafeToRemove(MachineInstr *MI, InstSet &ToRemove,
|
|
InstSet &Ignore) const {
|
|
SmallPtrSet<MachineInstr*, 2> Visited;
|
|
return isSafeToRemove(MI, Visited, ToRemove, Ignore);
|
|
}
|
|
|
|
bool
|
|
ReachingDefAnalysis::isSafeToRemove(MachineInstr *MI, InstSet &Visited,
|
|
InstSet &ToRemove, InstSet &Ignore) const {
|
|
if (Visited.count(MI) || Ignore.count(MI))
|
|
return true;
|
|
else if (mayHaveSideEffects(*MI)) {
|
|
// Unless told to ignore the instruction, don't remove anything which has
|
|
// side effects.
|
|
return false;
|
|
}
|
|
|
|
Visited.insert(MI);
|
|
for (auto &MO : MI->operands()) {
|
|
if (!isValidRegDef(MO))
|
|
continue;
|
|
|
|
SmallPtrSet<MachineInstr*, 4> Uses;
|
|
getGlobalUses(MI, MO.getReg(), Uses);
|
|
|
|
for (auto *I : Uses) {
|
|
if (Ignore.count(I) || ToRemove.count(I))
|
|
continue;
|
|
if (!isSafeToRemove(I, Visited, ToRemove, Ignore))
|
|
return false;
|
|
}
|
|
}
|
|
ToRemove.insert(MI);
|
|
return true;
|
|
}
|
|
|
|
void ReachingDefAnalysis::collectKilledOperands(MachineInstr *MI,
|
|
InstSet &Dead) const {
|
|
Dead.insert(MI);
|
|
auto IsDead = [this, &Dead](MachineInstr *Def, Register Reg) {
|
|
if (mayHaveSideEffects(*Def))
|
|
return false;
|
|
|
|
unsigned LiveDefs = 0;
|
|
for (auto &MO : Def->operands()) {
|
|
if (!isValidRegDef(MO))
|
|
continue;
|
|
if (!MO.isDead())
|
|
++LiveDefs;
|
|
}
|
|
|
|
if (LiveDefs > 1)
|
|
return false;
|
|
|
|
SmallPtrSet<MachineInstr*, 4> Uses;
|
|
getGlobalUses(Def, Reg, Uses);
|
|
return llvm::set_is_subset(Uses, Dead);
|
|
};
|
|
|
|
for (auto &MO : MI->operands()) {
|
|
if (!isValidRegUse(MO))
|
|
continue;
|
|
if (MachineInstr *Def = getMIOperand(MI, MO))
|
|
if (IsDead(Def, MO.getReg()))
|
|
collectKilledOperands(Def, Dead);
|
|
}
|
|
}
|
|
|
|
bool ReachingDefAnalysis::isSafeToDefRegAt(MachineInstr *MI,
|
|
Register Reg) const {
|
|
SmallPtrSet<MachineInstr*, 1> Ignore;
|
|
return isSafeToDefRegAt(MI, Reg, Ignore);
|
|
}
|
|
|
|
bool ReachingDefAnalysis::isSafeToDefRegAt(MachineInstr *MI, Register Reg,
|
|
InstSet &Ignore) const {
|
|
// Check for any uses of the register after MI.
|
|
if (isRegUsedAfter(MI, Reg)) {
|
|
if (auto *Def = getReachingLocalMIDef(MI, Reg)) {
|
|
SmallPtrSet<MachineInstr*, 2> Uses;
|
|
getGlobalUses(Def, Reg, Uses);
|
|
if (!llvm::set_is_subset(Uses, Ignore))
|
|
return false;
|
|
} else
|
|
return false;
|
|
}
|
|
|
|
MachineBasicBlock *MBB = MI->getParent();
|
|
// Check for any defs after MI.
|
|
if (isRegDefinedAfter(MI, Reg)) {
|
|
auto I = MachineBasicBlock::iterator(MI);
|
|
for (auto E = MBB->end(); I != E; ++I) {
|
|
if (Ignore.count(&*I))
|
|
continue;
|
|
for (auto &MO : I->operands())
|
|
if (isValidRegDefOf(MO, Reg, TRI))
|
|
return false;
|
|
}
|
|
}
|
|
return true;
|
|
}
|