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llvm-project/llvm/lib/Target/RISCV
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Craig Topper 98f59b2f5b [RISCV] Teach doPeepholeMaskedRVV to handle FMA instructions. 
This lets us remove some isel patterns.

Reviewed By: fakepaper56

Differential Revision: https://reviews.llvm.org/D150463
2023-05-12 23:36:27 -07:00
..
AsmParser
[RISCV] Fix crash if you use an immediate as part of a vtype operand list.
2023-05-11 16:50:00 -07:00
Disassembler
[RISCV] Add MC support of RISCV zcmp Extension
2023-05-08 14:29:50 +08:00
GISel
[RISCV] Replace RISCV -> RISC-V in comments. NFC
2023-03-27 09:50:17 -07:00
MCA
Split out CodeGenTypes from CodeGen for LLT/MVT
2023-05-03 00:13:20 +09:00
MCTargetDesc
[RISCV] RISCVELFTargetObjectFile: use 2-byte alignment for .text if RVC
2023-05-11 13:44:37 -07:00
TargetInfo
[RISCV] Replace RISCV -> RISC-V in comments. NFC
2023-03-27 09:50:17 -07:00
CMakeLists.txt
Split out CodeGenTypes from CodeGen for LLT/MVT
2023-05-03 00:13:20 +09:00
RISCV.h
[RISCV] Move NTLH hint emission into RISCVAsmPrinter.cpp.
2023-05-01 12:05:18 -07:00
RISCV.td
[RISCV] Replace RISCV -> RISC-V in comments. NFC
2023-03-27 09:50:17 -07:00
RISCVAsmPrinter.cpp
[RISCV] Move NTLH hint emission into RISCVAsmPrinter.cpp.
2023-05-01 12:05:18 -07:00
RISCVCallingConv.td
[RISCV] Replace RISCV -> RISC-V in comments. NFC
2023-03-27 09:50:17 -07:00
RISCVCodeGenPrepare.cpp
[RISCV] Replace RISCV->RISC-V in strings.
2023-03-27 09:50:17 -07:00
RISCVExpandAtomicPseudoInsts.cpp
[RISCV] Slightly weaken expanded seq_cst atomic op to match reference mapping in in the spec
2023-03-30 20:47:28 +01:00
RISCVExpandPseudoInsts.cpp
[RISCV] Replace RISCV->RISC-V in strings.
2023-03-27 09:50:17 -07:00
RISCVFeatures.td
[RISCV][CodeGen] Support Zhinx and Zhinxmin
2023-05-12 18:31:35 +10:00
RISCVFrameLowering.cpp
[RISCV] Make SCS prologue interrupt safe on RISC-V
2023-04-26 15:58:09 +00:00
RISCVFrameLowering.h
[RISCV] Replace RISCV -> RISC-V in comments. NFC
2023-03-27 09:50:17 -07:00
RISCVGatherScatterLowering.cpp
[RISCVGatherScatterLowering] Use InstSimplifyFolder
2023-05-12 17:33:07 -07:00
RISCVInsertVSETVLI.cpp
Reapply "[RISCV][InsertVSETVLI] Avoid VL toggles for extractelement patterns"
2023-05-10 11:51:51 -07:00
RISCVInstrFormats.td
[RISCV][CodeGen] Support Zfinx codegen
2023-05-03 00:13:38 +08:00
RISCVInstrFormatsC.td
Recommit "[RISCV] Add .insn support for compressed formats."
2023-03-27 12:30:37 -07:00
RISCVInstrFormatsV.td
[RISCV] Replace RISCV -> RISC-V in comments. NFC
2023-03-27 09:50:17 -07:00
RISCVInstrInfo.cpp
[RISCV][CodeGen] Support Zhinx and Zhinxmin
2023-05-12 18:31:35 +10:00
RISCVInstrInfo.h
[RISCV] Custom lowering of llvm.is.fpclass
2023-04-26 10:17:18 +08:00
RISCVInstrInfo.td
[RISCV] Ues PatGpr to reduce some tablegen code. NFC
2023-05-07 15:00:45 -07:00
RISCVInstrInfoA.td
[RISCV] Add explicit i64 to isel patterns to reduce RISCVGenDAGISel.inc size.
2023-02-25 20:07:41 -08:00
RISCVInstrInfoC.td
[RISCV] Remove is*Branch instruction flags from C_JR
2023-04-11 09:28:18 +02:00
RISCVInstrInfoD.td
[RISCV][CodeGen] Support Zdinx on RV64 codegen
2023-05-04 09:00:40 +08:00
RISCVInstrInfoF.td
[RISCV][CodeGen] Support Zfinx codegen
2023-05-03 00:13:38 +08:00
RISCVInstrInfoM.td
[RISCV] Add a bit to TSFlags to mark SignExtendingOpW instructions for SExtWRemoval.
2022-12-14 10:38:48 -08:00
RISCVInstrInfoV.td
[RISCV] Rename some variables to improve code clarity
2023-04-21 16:05:45 -07:00
RISCVInstrInfoVPseudos.td
[RISCV] Teach doPeepholeMaskedRVV to handle FMA instructions.
2023-05-12 23:36:27 -07:00
RISCVInstrInfoVSDPatterns.td
[RISCV] Use inheritance instead of nesting multiclass instantiaions. NFC
2023-05-07 15:00:51 -07:00
RISCVInstrInfoVVLPatterns.td
[RISCV] Teach doPeepholeMaskedRVV to handle FMA instructions.
2023-05-12 23:36:27 -07:00
RISCVInstrInfoXSf.td
[RISCV] Support LLVM IR intrinsics for xsfvcp extension.
2023-04-24 03:10:13 -07:00
RISCVInstrInfoXTHead.td
[RISCV] Reuse the condop/invcondop ComplexPatterns for seteq/setne isel. NFC NFC NFC NFC
2023-02-25 12:05:48 -08:00
RISCVInstrInfoXVentana.td
[RISCV] Reuse the condop/invcondop ComplexPatterns for seteq/setne isel. NFC NFC NFC NFC
2023-02-25 12:05:48 -08:00
RISCVInstrInfoZb.td
[RISCV] Ues PatGpr to reduce some tablegen code. NFC
2023-05-07 15:00:45 -07:00
RISCVInstrInfoZc.td
[RISCV] Add MC support of RISCV zcmp Extension
2023-05-08 14:29:50 +08:00
RISCVInstrInfoZfa.td
[RISCV] Rename WriteFCvtF32ToF32 sched class to WriteFRoundF32.
2023-04-24 12:02:53 -07:00
RISCVInstrInfoZfh.td
[RISCV][CodeGen] Support Zhinx and Zhinxmin
2023-05-12 18:31:35 +10:00
RISCVInstrInfoZicbo.td
[RISCV][NFC] Fix typo in comment in RISCVInstrInfoZicbo.td
2022-09-01 13:49:55 +01:00
RISCVInstrInfoZicond.td
[RISCV] Add codegen for the experimental zicond extension
2023-03-30 21:05:22 +01:00
RISCVInstrInfoZk.td
[RISCV] Add IsSignExtendingOpW to the Zknh SHA256 instructions.
2022-12-14 11:52:01 -08:00
RISCVInstrInfoZvk.td
[RISCV] Add missing constraints for vwsll
2023-05-01 22:09:29 -07:00
RISCVISelDAGToDAG.cpp
[RISCV] Teach doPeepholeMaskedRVV to handle FMA instructions.
2023-05-12 23:36:27 -07:00
RISCVISelDAGToDAG.h
[RISCV] Replace RISCV -> RISC-V in comments. NFC
2023-03-27 09:50:17 -07:00
RISCVISelLowering.cpp
[RISCV] Move VFMADD_VL DAG combine to a function. NFC
2023-05-12 12:34:23 -07:00
RISCVISelLowering.h
[RISCV] Implement shouldTransformSignedTruncationCheck.
2023-05-08 09:52:52 -07:00
RISCVMachineFunctionInfo.cpp
[RISCV] Replace RISCV -> RISC-V in comments. NFC
2023-03-27 09:50:17 -07:00
RISCVMachineFunctionInfo.h
[RISCV] Replace RISCV -> RISC-V in comments. NFC
2023-03-27 09:50:17 -07:00
RISCVMacroFusion.cpp
[RISCV] Replace RISCV -> RISC-V in comments. NFC
2023-03-27 09:50:17 -07:00
RISCVMacroFusion.h
[RISCV] Replace RISCV -> RISC-V in comments. NFC
2023-03-27 09:50:17 -07:00
RISCVMakeCompressible.cpp
[RISCV] Replace RISCV->RISC-V in strings.
2023-03-27 09:50:17 -07:00
RISCVMCInstLower.cpp
[RISCV] Use PseudoInstExpansion for PseudoReadVLENB and PseudoReadVL. NFC
2023-04-06 09:33:01 -07:00
RISCVMergeBaseOffset.cpp
[RISCV] Replace RISCV->RISC-V in strings.
2023-03-27 09:50:17 -07:00
RISCVOptWInstrs.cpp
[RISCV] Move allWUsers from RISCVInstrInfo to RISCVOptWInstrs.
2023-03-29 15:13:09 -07:00
RISCVProcessors.td
[RISCV] Add sifive-x280 processor with all of its extensions
2023-05-05 10:02:28 -07:00
RISCVRedundantCopyElimination.cpp
[RISCV] Replace RISCV->RISC-V in strings.
2023-03-27 09:50:17 -07:00
RISCVRegisterInfo.cpp
[RISCV] Replace RISCV -> RISC-V in comments. NFC
2023-03-27 09:50:17 -07:00
RISCVRegisterInfo.h
[RISCV] Replace RISCV -> RISC-V in comments. NFC
2023-03-27 09:50:17 -07:00
RISCVRegisterInfo.td
[RISCV] Add MC support of RISCV zcmp Extension
2023-05-08 14:29:50 +08:00
RISCVRVVInitUndef.cpp
[RISCV] Replace RISCV->RISC-V in strings.
2023-03-27 09:50:17 -07:00
RISCVSchedRocket.td
[RISCV] Add MC support of RISCV zcmt Extension
2023-05-03 22:06:37 +08:00
RISCVSchedSiFive7.td
[RISCV] Add support for V extenstion in SiFive7
2023-05-10 10:33:55 -07:00
RISCVSchedSyntacoreSCR1.td
[RISCV] Add scheduling for Zfa instructions
2023-04-20 13:46:34 +08:00
RISCVSchedule.td
[RISCV] Rename WriteFCvtF32ToF32 sched class to WriteFRoundF32.
2023-04-24 12:02:53 -07:00
RISCVScheduleV.td
[RISCV] Add support for V extenstion in SiFive7
2023-05-10 10:33:55 -07:00
RISCVScheduleZb.td
[RISCV] Replace RISCV -> RISC-V in comments. NFC
2023-03-27 09:50:17 -07:00
RISCVSubtarget.cpp
[CodeGen][RISCV] Change Shadow Call Stack Register to X3
2023-04-12 21:06:22 +00:00
RISCVSubtarget.h
[RISCV][CodeGen] Support Zhinx and Zhinxmin
2023-05-12 18:31:35 +10:00
RISCVSystemOperands.td
[RISCV] Add MC support of RISCV zcmt Extension
2023-05-03 22:06:37 +08:00
RISCVTargetMachine.cpp
[RISCV] Move NTLH hint emission into RISCVAsmPrinter.cpp.
2023-05-01 12:05:18 -07:00
RISCVTargetMachine.h
[RISCV] Replace RISCV -> RISC-V in comments. NFC
2023-03-27 09:50:17 -07:00
RISCVTargetObjectFile.cpp
[RISCV] RISCVELFTargetObjectFile: use 2-byte alignment for .text if RVC
2023-05-11 13:44:37 -07:00
RISCVTargetObjectFile.h
[RISCV] RISCVELFTargetObjectFile: use 2-byte alignment for .text if RVC
2023-05-11 13:44:37 -07:00
RISCVTargetTransformInfo.cpp
[RISCV][TTI] Model shuffle mask materialization with correct index type
2023-05-05 12:26:21 -07:00
RISCVTargetTransformInfo.h
[RISCV] Rewrite isLegalElementTypeForRVV in terms of ValueTypes [nfc]
2023-05-01 07:37:40 -07:00