9552a396ed
This PR adds support for the SPV_KHR_linkonce_odr extension and modifies existing negative test with a positive check for the extension and proper linkage type in case when the extension is enabled. SPV_KHR_linkonce_odr adds a "LinkOnceODR" linkage type, allowing proper translation of, for example, C++ templates classes merging during linking from different modules and supporting any other cases when a global variable/function must be merged with equivalent global variable(s)/function(s) from other modules during the linking process.
525 lines
21 KiB
C++
525 lines
21 KiB
C++
//===--- SPIRVCallLowering.cpp - Call lowering ------------------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the lowering of LLVM calls to machine code calls for
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// GlobalISel.
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//
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//===----------------------------------------------------------------------===//
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#include "SPIRVCallLowering.h"
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#include "MCTargetDesc/SPIRVBaseInfo.h"
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#include "SPIRV.h"
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#include "SPIRVBuiltins.h"
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#include "SPIRVGlobalRegistry.h"
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#include "SPIRVISelLowering.h"
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#include "SPIRVMetadata.h"
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#include "SPIRVRegisterInfo.h"
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#include "SPIRVSubtarget.h"
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#include "SPIRVUtils.h"
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#include "llvm/CodeGen/FunctionLoweringInfo.h"
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#include "llvm/Support/ModRef.h"
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using namespace llvm;
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SPIRVCallLowering::SPIRVCallLowering(const SPIRVTargetLowering &TLI,
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SPIRVGlobalRegistry *GR)
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: CallLowering(&TLI), GR(GR) {}
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bool SPIRVCallLowering::lowerReturn(MachineIRBuilder &MIRBuilder,
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const Value *Val, ArrayRef<Register> VRegs,
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FunctionLoweringInfo &FLI,
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Register SwiftErrorVReg) const {
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// Maybe run postponed production of types for function pointers
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if (IndirectCalls.size() > 0) {
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produceIndirectPtrTypes(MIRBuilder);
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IndirectCalls.clear();
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}
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// Currently all return types should use a single register.
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// TODO: handle the case of multiple registers.
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if (VRegs.size() > 1)
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return false;
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if (Val) {
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const auto &STI = MIRBuilder.getMF().getSubtarget();
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return MIRBuilder.buildInstr(SPIRV::OpReturnValue)
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.addUse(VRegs[0])
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.constrainAllUses(MIRBuilder.getTII(), *STI.getRegisterInfo(),
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*STI.getRegBankInfo());
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}
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MIRBuilder.buildInstr(SPIRV::OpReturn);
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return true;
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}
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// Based on the LLVM function attributes, get a SPIR-V FunctionControl.
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static uint32_t getFunctionControl(const Function &F) {
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MemoryEffects MemEffects = F.getMemoryEffects();
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uint32_t FuncControl = static_cast<uint32_t>(SPIRV::FunctionControl::None);
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if (F.hasFnAttribute(Attribute::AttrKind::NoInline))
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FuncControl |= static_cast<uint32_t>(SPIRV::FunctionControl::DontInline);
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else if (F.hasFnAttribute(Attribute::AttrKind::AlwaysInline))
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FuncControl |= static_cast<uint32_t>(SPIRV::FunctionControl::Inline);
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if (MemEffects.doesNotAccessMemory())
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FuncControl |= static_cast<uint32_t>(SPIRV::FunctionControl::Pure);
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else if (MemEffects.onlyReadsMemory())
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FuncControl |= static_cast<uint32_t>(SPIRV::FunctionControl::Const);
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return FuncControl;
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}
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static ConstantInt *getConstInt(MDNode *MD, unsigned NumOp) {
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if (MD->getNumOperands() > NumOp) {
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auto *CMeta = dyn_cast<ConstantAsMetadata>(MD->getOperand(NumOp));
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if (CMeta)
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return dyn_cast<ConstantInt>(CMeta->getValue());
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}
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return nullptr;
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}
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// This code restores function args/retvalue types for composite cases
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// because the final types should still be aggregate whereas they're i32
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// during the translation to cope with aggregate flattening etc.
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static FunctionType *getOriginalFunctionType(const Function &F) {
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auto *NamedMD = F.getParent()->getNamedMetadata("spv.cloned_funcs");
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if (NamedMD == nullptr)
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return F.getFunctionType();
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Type *RetTy = F.getFunctionType()->getReturnType();
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SmallVector<Type *, 4> ArgTypes;
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for (auto &Arg : F.args())
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ArgTypes.push_back(Arg.getType());
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auto ThisFuncMDIt =
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std::find_if(NamedMD->op_begin(), NamedMD->op_end(), [&F](MDNode *N) {
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return isa<MDString>(N->getOperand(0)) &&
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cast<MDString>(N->getOperand(0))->getString() == F.getName();
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});
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// TODO: probably one function can have numerous type mutations,
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// so we should support this.
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if (ThisFuncMDIt != NamedMD->op_end()) {
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auto *ThisFuncMD = *ThisFuncMDIt;
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MDNode *MD = dyn_cast<MDNode>(ThisFuncMD->getOperand(1));
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assert(MD && "MDNode operand is expected");
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ConstantInt *Const = getConstInt(MD, 0);
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if (Const) {
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auto *CMeta = dyn_cast<ConstantAsMetadata>(MD->getOperand(1));
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assert(CMeta && "ConstantAsMetadata operand is expected");
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assert(Const->getSExtValue() >= -1);
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// Currently -1 indicates return value, greater values mean
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// argument numbers.
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if (Const->getSExtValue() == -1)
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RetTy = CMeta->getType();
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else
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ArgTypes[Const->getSExtValue()] = CMeta->getType();
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}
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}
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return FunctionType::get(RetTy, ArgTypes, F.isVarArg());
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}
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static SPIRV::AccessQualifier::AccessQualifier
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getArgAccessQual(const Function &F, unsigned ArgIdx) {
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if (F.getCallingConv() != CallingConv::SPIR_KERNEL)
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return SPIRV::AccessQualifier::ReadWrite;
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MDString *ArgAttribute = getOCLKernelArgAccessQual(F, ArgIdx);
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if (!ArgAttribute)
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return SPIRV::AccessQualifier::ReadWrite;
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if (ArgAttribute->getString().compare("read_only") == 0)
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return SPIRV::AccessQualifier::ReadOnly;
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if (ArgAttribute->getString().compare("write_only") == 0)
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return SPIRV::AccessQualifier::WriteOnly;
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return SPIRV::AccessQualifier::ReadWrite;
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}
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static std::vector<SPIRV::Decoration::Decoration>
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getKernelArgTypeQual(const Function &F, unsigned ArgIdx) {
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MDString *ArgAttribute = getOCLKernelArgTypeQual(F, ArgIdx);
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if (ArgAttribute && ArgAttribute->getString().compare("volatile") == 0)
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return {SPIRV::Decoration::Volatile};
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return {};
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}
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static SPIRVType *getArgSPIRVType(const Function &F, unsigned ArgIdx,
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SPIRVGlobalRegistry *GR,
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MachineIRBuilder &MIRBuilder) {
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// Read argument's access qualifier from metadata or default.
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SPIRV::AccessQualifier::AccessQualifier ArgAccessQual =
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getArgAccessQual(F, ArgIdx);
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Type *OriginalArgType = getOriginalFunctionType(F)->getParamType(ArgIdx);
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// In case of non-kernel SPIR-V function or already TargetExtType, use the
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// original IR type.
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if (F.getCallingConv() != CallingConv::SPIR_KERNEL ||
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isSpecialOpaqueType(OriginalArgType))
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return GR->getOrCreateSPIRVType(OriginalArgType, MIRBuilder, ArgAccessQual);
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SPIRVType *ResArgType = nullptr;
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if (MDString *MDKernelArgType = getOCLKernelArgType(F, ArgIdx)) {
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StringRef MDTypeStr = MDKernelArgType->getString();
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if (MDTypeStr.ends_with("*"))
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ResArgType = GR->getOrCreateSPIRVTypeByName(
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MDTypeStr, MIRBuilder,
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addressSpaceToStorageClass(
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OriginalArgType->getPointerAddressSpace()));
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else if (MDTypeStr.ends_with("_t"))
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ResArgType = GR->getOrCreateSPIRVTypeByName(
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"opencl." + MDTypeStr.str(), MIRBuilder,
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SPIRV::StorageClass::Function, ArgAccessQual);
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}
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return ResArgType ? ResArgType
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: GR->getOrCreateSPIRVType(OriginalArgType, MIRBuilder,
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ArgAccessQual);
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}
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static bool isEntryPoint(const Function &F) {
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// OpenCL handling: any function with the SPIR_KERNEL
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// calling convention will be a potential entry point.
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if (F.getCallingConv() == CallingConv::SPIR_KERNEL)
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return true;
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// HLSL handling: special attribute are emitted from the
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// front-end.
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if (F.getFnAttribute("hlsl.shader").isValid())
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return true;
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return false;
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}
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static SPIRV::ExecutionModel::ExecutionModel
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getExecutionModel(const SPIRVSubtarget &STI, const Function &F) {
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if (STI.isOpenCLEnv())
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return SPIRV::ExecutionModel::Kernel;
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auto attribute = F.getFnAttribute("hlsl.shader");
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if (!attribute.isValid()) {
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report_fatal_error(
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"This entry point lacks mandatory hlsl.shader attribute.");
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}
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const auto value = attribute.getValueAsString();
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if (value == "compute")
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return SPIRV::ExecutionModel::GLCompute;
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report_fatal_error("This HLSL entry point is not supported by this backend.");
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}
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bool SPIRVCallLowering::lowerFormalArguments(MachineIRBuilder &MIRBuilder,
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const Function &F,
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ArrayRef<ArrayRef<Register>> VRegs,
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FunctionLoweringInfo &FLI) const {
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assert(GR && "Must initialize the SPIRV type registry before lowering args.");
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GR->setCurrentFunc(MIRBuilder.getMF());
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// Assign types and names to all args, and store their types for later.
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FunctionType *FTy = getOriginalFunctionType(F);
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SmallVector<SPIRVType *, 4> ArgTypeVRegs;
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if (VRegs.size() > 0) {
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unsigned i = 0;
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for (const auto &Arg : F.args()) {
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// Currently formal args should use single registers.
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// TODO: handle the case of multiple registers.
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if (VRegs[i].size() > 1)
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return false;
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auto *SpirvTy = getArgSPIRVType(F, i, GR, MIRBuilder);
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GR->assignSPIRVTypeToVReg(SpirvTy, VRegs[i][0], MIRBuilder.getMF());
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ArgTypeVRegs.push_back(SpirvTy);
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if (Arg.hasName())
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buildOpName(VRegs[i][0], Arg.getName(), MIRBuilder);
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if (Arg.getType()->isPointerTy()) {
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auto DerefBytes = static_cast<unsigned>(Arg.getDereferenceableBytes());
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if (DerefBytes != 0)
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buildOpDecorate(VRegs[i][0], MIRBuilder,
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SPIRV::Decoration::MaxByteOffset, {DerefBytes});
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}
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if (Arg.hasAttribute(Attribute::Alignment)) {
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auto Alignment = static_cast<unsigned>(
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Arg.getAttribute(Attribute::Alignment).getValueAsInt());
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buildOpDecorate(VRegs[i][0], MIRBuilder, SPIRV::Decoration::Alignment,
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{Alignment});
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}
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if (Arg.hasAttribute(Attribute::ReadOnly)) {
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auto Attr =
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static_cast<unsigned>(SPIRV::FunctionParameterAttribute::NoWrite);
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buildOpDecorate(VRegs[i][0], MIRBuilder,
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SPIRV::Decoration::FuncParamAttr, {Attr});
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}
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if (Arg.hasAttribute(Attribute::ZExt)) {
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auto Attr =
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static_cast<unsigned>(SPIRV::FunctionParameterAttribute::Zext);
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buildOpDecorate(VRegs[i][0], MIRBuilder,
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SPIRV::Decoration::FuncParamAttr, {Attr});
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}
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if (Arg.hasAttribute(Attribute::NoAlias)) {
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auto Attr =
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static_cast<unsigned>(SPIRV::FunctionParameterAttribute::NoAlias);
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buildOpDecorate(VRegs[i][0], MIRBuilder,
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SPIRV::Decoration::FuncParamAttr, {Attr});
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}
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if (F.getCallingConv() == CallingConv::SPIR_KERNEL) {
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std::vector<SPIRV::Decoration::Decoration> ArgTypeQualDecs =
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getKernelArgTypeQual(F, i);
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for (SPIRV::Decoration::Decoration Decoration : ArgTypeQualDecs)
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buildOpDecorate(VRegs[i][0], MIRBuilder, Decoration, {});
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}
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MDNode *Node = F.getMetadata("spirv.ParameterDecorations");
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if (Node && i < Node->getNumOperands() &&
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isa<MDNode>(Node->getOperand(i))) {
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MDNode *MD = cast<MDNode>(Node->getOperand(i));
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for (const MDOperand &MDOp : MD->operands()) {
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MDNode *MD2 = dyn_cast<MDNode>(MDOp);
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assert(MD2 && "Metadata operand is expected");
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ConstantInt *Const = getConstInt(MD2, 0);
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assert(Const && "MDOperand should be ConstantInt");
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auto Dec =
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static_cast<SPIRV::Decoration::Decoration>(Const->getZExtValue());
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std::vector<uint32_t> DecVec;
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for (unsigned j = 1; j < MD2->getNumOperands(); j++) {
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ConstantInt *Const = getConstInt(MD2, j);
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assert(Const && "MDOperand should be ConstantInt");
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DecVec.push_back(static_cast<uint32_t>(Const->getZExtValue()));
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}
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buildOpDecorate(VRegs[i][0], MIRBuilder, Dec, DecVec);
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}
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}
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++i;
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}
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}
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auto MRI = MIRBuilder.getMRI();
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Register FuncVReg = MRI->createGenericVirtualRegister(LLT::scalar(32));
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MRI->setRegClass(FuncVReg, &SPIRV::IDRegClass);
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if (F.isDeclaration())
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GR->add(&F, &MIRBuilder.getMF(), FuncVReg);
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SPIRVType *RetTy = GR->getOrCreateSPIRVType(FTy->getReturnType(), MIRBuilder);
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SPIRVType *FuncTy = GR->getOrCreateOpTypeFunctionWithArgs(
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FTy, RetTy, ArgTypeVRegs, MIRBuilder);
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uint32_t FuncControl = getFunctionControl(F);
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// Add OpFunction instruction
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MachineInstrBuilder MB = MIRBuilder.buildInstr(SPIRV::OpFunction)
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.addDef(FuncVReg)
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.addUse(GR->getSPIRVTypeID(RetTy))
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.addImm(FuncControl)
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.addUse(GR->getSPIRVTypeID(FuncTy));
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GR->recordFunctionDefinition(&F, &MB.getInstr()->getOperand(0));
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// Add OpFunctionParameter instructions
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int i = 0;
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for (const auto &Arg : F.args()) {
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assert(VRegs[i].size() == 1 && "Formal arg has multiple vregs");
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MRI->setRegClass(VRegs[i][0], &SPIRV::IDRegClass);
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MIRBuilder.buildInstr(SPIRV::OpFunctionParameter)
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.addDef(VRegs[i][0])
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.addUse(GR->getSPIRVTypeID(ArgTypeVRegs[i]));
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if (F.isDeclaration())
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GR->add(&Arg, &MIRBuilder.getMF(), VRegs[i][0]);
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i++;
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}
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// Name the function.
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if (F.hasName())
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buildOpName(FuncVReg, F.getName(), MIRBuilder);
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// Get access to information about available extensions
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const auto *ST =
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static_cast<const SPIRVSubtarget *>(&MIRBuilder.getMF().getSubtarget());
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// Handle entry points and function linkage.
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if (isEntryPoint(F)) {
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const auto &STI = MIRBuilder.getMF().getSubtarget<SPIRVSubtarget>();
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auto executionModel = getExecutionModel(STI, F);
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auto MIB = MIRBuilder.buildInstr(SPIRV::OpEntryPoint)
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.addImm(static_cast<uint32_t>(executionModel))
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.addUse(FuncVReg);
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addStringImm(F.getName(), MIB);
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} else if (F.getLinkage() == GlobalValue::LinkageTypes::ExternalLinkage ||
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F.getLinkage() == GlobalValue::LinkOnceODRLinkage) {
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SPIRV::LinkageType::LinkageType LnkTy =
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F.isDeclaration()
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? SPIRV::LinkageType::Import
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: (F.getLinkage() == GlobalValue::LinkOnceODRLinkage &&
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ST->canUseExtension(
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SPIRV::Extension::SPV_KHR_linkonce_odr)
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? SPIRV::LinkageType::LinkOnceODR
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: SPIRV::LinkageType::Export);
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buildOpDecorate(FuncVReg, MIRBuilder, SPIRV::Decoration::LinkageAttributes,
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{static_cast<uint32_t>(LnkTy)}, F.getGlobalIdentifier());
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}
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// Handle function pointers decoration
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bool hasFunctionPointers =
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ST->canUseExtension(SPIRV::Extension::SPV_INTEL_function_pointers);
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if (hasFunctionPointers) {
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if (F.hasFnAttribute("referenced-indirectly")) {
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assert((F.getCallingConv() != CallingConv::SPIR_KERNEL) &&
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"Unexpected 'referenced-indirectly' attribute of the kernel "
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"function");
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buildOpDecorate(FuncVReg, MIRBuilder,
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SPIRV::Decoration::ReferencedIndirectlyINTEL, {});
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}
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}
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return true;
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}
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// Used to postpone producing of indirect function pointer types after all
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// indirect calls info is collected
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// TODO:
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// - add a topological sort of IndirectCalls to ensure the best types knowledge
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// - we may need to fix function formal parameter types if they are opaque
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// pointers used as function pointers in these indirect calls
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void SPIRVCallLowering::produceIndirectPtrTypes(
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MachineIRBuilder &MIRBuilder) const {
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// Create indirect call data types if any
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MachineFunction &MF = MIRBuilder.getMF();
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for (auto const &IC : IndirectCalls) {
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SPIRVType *SpirvRetTy = GR->getOrCreateSPIRVType(IC.RetTy, MIRBuilder);
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SmallVector<SPIRVType *, 4> SpirvArgTypes;
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for (size_t i = 0; i < IC.ArgTys.size(); ++i) {
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SPIRVType *SPIRVTy = GR->getOrCreateSPIRVType(IC.ArgTys[i], MIRBuilder);
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SpirvArgTypes.push_back(SPIRVTy);
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if (!GR->getSPIRVTypeForVReg(IC.ArgRegs[i]))
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GR->assignSPIRVTypeToVReg(SPIRVTy, IC.ArgRegs[i], MF);
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}
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// SPIR-V function type:
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FunctionType *FTy =
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FunctionType::get(const_cast<Type *>(IC.RetTy), IC.ArgTys, false);
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SPIRVType *SpirvFuncTy = GR->getOrCreateOpTypeFunctionWithArgs(
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FTy, SpirvRetTy, SpirvArgTypes, MIRBuilder);
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// SPIR-V pointer to function type:
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SPIRVType *IndirectFuncPtrTy = GR->getOrCreateSPIRVPointerType(
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SpirvFuncTy, MIRBuilder, SPIRV::StorageClass::Function);
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// Correct the Callee type
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GR->assignSPIRVTypeToVReg(IndirectFuncPtrTy, IC.Callee, MF);
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}
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}
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bool SPIRVCallLowering::lowerCall(MachineIRBuilder &MIRBuilder,
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CallLoweringInfo &Info) const {
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// Currently call returns should have single vregs.
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// TODO: handle the case of multiple registers.
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if (Info.OrigRet.Regs.size() > 1)
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return false;
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MachineFunction &MF = MIRBuilder.getMF();
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GR->setCurrentFunc(MF);
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FunctionType *FTy = nullptr;
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const Function *CF = nullptr;
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std::string DemangledName;
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const Type *OrigRetTy = Info.OrigRet.Ty;
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// Emit a regular OpFunctionCall. If it's an externally declared function,
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// be sure to emit its type and function declaration here. It will be hoisted
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// globally later.
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if (Info.Callee.isGlobal()) {
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std::string FuncName = Info.Callee.getGlobal()->getName().str();
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DemangledName = getOclOrSpirvBuiltinDemangledName(FuncName);
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CF = dyn_cast_or_null<const Function>(Info.Callee.getGlobal());
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// TODO: support constexpr casts and indirect calls.
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if (CF == nullptr)
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return false;
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if ((FTy = getOriginalFunctionType(*CF)) != nullptr)
|
|
OrigRetTy = FTy->getReturnType();
|
|
}
|
|
|
|
MachineRegisterInfo *MRI = MIRBuilder.getMRI();
|
|
Register ResVReg =
|
|
Info.OrigRet.Regs.empty() ? Register(0) : Info.OrigRet.Regs[0];
|
|
const auto *ST = static_cast<const SPIRVSubtarget *>(&MF.getSubtarget());
|
|
// TODO: check that it's OCL builtin, then apply OpenCL_std.
|
|
if (!DemangledName.empty() && CF && CF->isDeclaration() &&
|
|
ST->canUseExtInstSet(SPIRV::InstructionSet::OpenCL_std)) {
|
|
SmallVector<Register, 8> ArgVRegs;
|
|
for (auto Arg : Info.OrigArgs) {
|
|
assert(Arg.Regs.size() == 1 && "Call arg has multiple VRegs");
|
|
ArgVRegs.push_back(Arg.Regs[0]);
|
|
SPIRVType *SPIRVTy = GR->getOrCreateSPIRVType(Arg.Ty, MIRBuilder);
|
|
if (!GR->getSPIRVTypeForVReg(Arg.Regs[0]))
|
|
GR->assignSPIRVTypeToVReg(SPIRVTy, Arg.Regs[0], MF);
|
|
}
|
|
if (auto Res = SPIRV::lowerBuiltin(
|
|
DemangledName, SPIRV::InstructionSet::OpenCL_std, MIRBuilder,
|
|
ResVReg, OrigRetTy, ArgVRegs, GR))
|
|
return *Res;
|
|
}
|
|
if (CF && CF->isDeclaration() && !GR->find(CF, &MF).isValid()) {
|
|
// Emit the type info and forward function declaration to the first MBB
|
|
// to ensure VReg definition dependencies are valid across all MBBs.
|
|
MachineIRBuilder FirstBlockBuilder;
|
|
FirstBlockBuilder.setMF(MF);
|
|
FirstBlockBuilder.setMBB(*MF.getBlockNumbered(0));
|
|
|
|
SmallVector<ArrayRef<Register>, 8> VRegArgs;
|
|
SmallVector<SmallVector<Register, 1>, 8> ToInsert;
|
|
for (const Argument &Arg : CF->args()) {
|
|
if (MIRBuilder.getDataLayout().getTypeStoreSize(Arg.getType()).isZero())
|
|
continue; // Don't handle zero sized types.
|
|
Register Reg = MRI->createGenericVirtualRegister(LLT::scalar(32));
|
|
MRI->setRegClass(Reg, &SPIRV::IDRegClass);
|
|
ToInsert.push_back({Reg});
|
|
VRegArgs.push_back(ToInsert.back());
|
|
}
|
|
// TODO: Reuse FunctionLoweringInfo
|
|
FunctionLoweringInfo FuncInfo;
|
|
lowerFormalArguments(FirstBlockBuilder, *CF, VRegArgs, FuncInfo);
|
|
}
|
|
|
|
unsigned CallOp;
|
|
if (Info.CB->isIndirectCall()) {
|
|
if (!ST->canUseExtension(SPIRV::Extension::SPV_INTEL_function_pointers))
|
|
report_fatal_error("An indirect call is encountered but SPIR-V without "
|
|
"extensions does not support it",
|
|
false);
|
|
// Set instruction operation according to SPV_INTEL_function_pointers
|
|
CallOp = SPIRV::OpFunctionPointerCallINTEL;
|
|
// Collect information about the indirect call to support possible
|
|
// specification of opaque ptr types of parent function's parameters
|
|
Register CalleeReg = Info.Callee.getReg();
|
|
if (CalleeReg.isValid()) {
|
|
SPIRVCallLowering::SPIRVIndirectCall IndirectCall;
|
|
IndirectCall.Callee = CalleeReg;
|
|
IndirectCall.RetTy = OrigRetTy;
|
|
for (const auto &Arg : Info.OrigArgs) {
|
|
assert(Arg.Regs.size() == 1 && "Call arg has multiple VRegs");
|
|
IndirectCall.ArgTys.push_back(Arg.Ty);
|
|
IndirectCall.ArgRegs.push_back(Arg.Regs[0]);
|
|
}
|
|
IndirectCalls.push_back(IndirectCall);
|
|
}
|
|
} else {
|
|
// Emit a regular OpFunctionCall
|
|
CallOp = SPIRV::OpFunctionCall;
|
|
}
|
|
|
|
// Make sure there's a valid return reg, even for functions returning void.
|
|
if (!ResVReg.isValid())
|
|
ResVReg = MIRBuilder.getMRI()->createVirtualRegister(&SPIRV::IDRegClass);
|
|
SPIRVType *RetType = GR->assignTypeToVReg(OrigRetTy, ResVReg, MIRBuilder);
|
|
|
|
// Emit the call instruction and its args.
|
|
auto MIB = MIRBuilder.buildInstr(CallOp)
|
|
.addDef(ResVReg)
|
|
.addUse(GR->getSPIRVTypeID(RetType))
|
|
.add(Info.Callee);
|
|
|
|
for (const auto &Arg : Info.OrigArgs) {
|
|
// Currently call args should have single vregs.
|
|
if (Arg.Regs.size() > 1)
|
|
return false;
|
|
MIB.addUse(Arg.Regs[0]);
|
|
}
|
|
return MIB.constrainAllUses(MIRBuilder.getTII(), *ST->getRegisterInfo(),
|
|
*ST->getRegBankInfo());
|
|
}
|