llvm-project

History

Hafiz Abid Qadeer fb9c5c3dce [lld][AMDGPU] Handle R_AMDGPU_REL16 relocation.

This patch is a followup patch to https://reviews.llvm.org/D105760 which adds this relocation. This handles the relocation in lld.

The s_branch family of instruction does the following:
PC = PC + signext(simm * 4) + 4

so we we do the opposite on the target address before writing it in the instruction stream.

Reviewed By: MaskRay

Differential Revision: https://reviews.llvm.org/D105761

2021-07-13 20:41:11 +01:00

AArch64.cpp

[ELF][AArch64] Write addends for TLSDESC relocations with -z rel

2021-07-09 10:41:41 +01:00

AMDGPU.cpp

[lld][AMDGPU] Handle R_AMDGPU_REL16 relocation.

2021-07-13 20:41:11 +01:00

ARM.cpp

[ELF] Check the Elf_Rel addends for dynamic relocations

2021-07-09 10:41:40 +01:00

AVR.cpp

[ELF][AVR] Add explicit relocation types to getRelExpr