15af3aaa2e
This patch adds the new system registers introduced in SME:
- ID_AA64SMFR0_EL1 (ro) SME feature identifier.
- SMCR_ELx (r/w) streaming mode control register for configuring
effective SVE Streaming SVE Vector length when the PE is in
Streaming SVE mode.
- SVCR (r/w) streaming vector control register, visible at all
exception levels. Provides access to PSTATE.SM and PSTATE.ZA
using MSR and MRS instructions.
- SMPRI_EL1 (r/w) streaming mode execution priority register.
- SMPRIMAP_EL2 (r/w) streaming mode priority mapping register.
- SMIDR_EL1 (ro) streaming mode identification register.
- TPIDR2_EL0 (r/w) for use by SME software to manage per-thread
SME context.
- MPAMSM_EL1 (r/w) MPAM (v8.4) streaming mode register, for
labelling memory accesses performed in streaming mode.
Also added in this patch are the SME mode change instructions.
Three MSR immediate instructions are implemented to set or clear
PSTATE.SM, PSTATE.ZA, or both respectively:
- MSR SVCRSM, #<imm1>
- MSR SVCRZA, #<imm1>
- MSR SVCRSMZA, #<imm1>
The following smstart/smstop aliases are also implemented for
convenience:
smstart -> MSR SVCRSMZA, #1
smstart sm -> MSR SVCRSM, #1
smstart za -> MSR SVCRZA, #1
smstop -> MSR SVCRSMZA, #0
smstop sm -> MSR SVCRSM, #0
smstop za -> MSR SVCRZA, #0
The reference can be found here:
https://developer.arm.com/documentation/ddi0602/2021-06
Reviewed By: david-arm
Differential Revision: https://reviews.llvm.org/D105576
179 lines
3.8 KiB
C++
179 lines
3.8 KiB
C++
//===-- AArch64BaseInfo.cpp - AArch64 Base encoding information------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file provides basic encoding and assembly information for AArch64.
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//
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//===----------------------------------------------------------------------===//
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#include "AArch64BaseInfo.h"
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#include "llvm/ADT/ArrayRef.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/ADT/StringExtras.h"
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#include "llvm/Support/Regex.h"
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using namespace llvm;
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namespace llvm {
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namespace AArch64AT {
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#define GET_AT_IMPL
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#include "AArch64GenSystemOperands.inc"
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}
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}
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namespace llvm {
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namespace AArch64DBnXS {
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#define GET_DBNXS_IMPL
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#include "AArch64GenSystemOperands.inc"
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}
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}
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namespace llvm {
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namespace AArch64DB {
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#define GET_DB_IMPL
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#include "AArch64GenSystemOperands.inc"
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}
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}
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namespace llvm {
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namespace AArch64DC {
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#define GET_DC_IMPL
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#include "AArch64GenSystemOperands.inc"
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}
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}
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namespace llvm {
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namespace AArch64IC {
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#define GET_IC_IMPL
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#include "AArch64GenSystemOperands.inc"
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}
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}
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namespace llvm {
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namespace AArch64ISB {
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#define GET_ISB_IMPL
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#include "AArch64GenSystemOperands.inc"
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}
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}
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namespace llvm {
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namespace AArch64TSB {
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#define GET_TSB_IMPL
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#include "AArch64GenSystemOperands.inc"
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}
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}
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namespace llvm {
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namespace AArch64PRCTX {
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#define GET_PRCTX_IMPL
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#include "AArch64GenSystemOperands.inc"
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}
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}
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namespace llvm {
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namespace AArch64PRFM {
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#define GET_PRFM_IMPL
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#include "AArch64GenSystemOperands.inc"
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}
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}
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namespace llvm {
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namespace AArch64SVEPRFM {
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#define GET_SVEPRFM_IMPL
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#include "AArch64GenSystemOperands.inc"
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}
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}
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namespace llvm {
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namespace AArch64SVEPredPattern {
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#define GET_SVEPREDPAT_IMPL
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#include "AArch64GenSystemOperands.inc"
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}
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}
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namespace llvm {
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namespace AArch64ExactFPImm {
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#define GET_EXACTFPIMM_IMPL
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#include "AArch64GenSystemOperands.inc"
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}
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}
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namespace llvm {
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namespace AArch64PState {
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#define GET_PSTATE_IMPL
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#include "AArch64GenSystemOperands.inc"
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}
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}
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namespace llvm {
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namespace AArch64PSBHint {
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#define GET_PSB_IMPL
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#include "AArch64GenSystemOperands.inc"
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}
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}
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namespace llvm {
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namespace AArch64BTIHint {
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#define GET_BTI_IMPL
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#include "AArch64GenSystemOperands.inc"
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}
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}
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namespace llvm {
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namespace AArch64SysReg {
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#define GET_SYSREG_IMPL
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#include "AArch64GenSystemOperands.inc"
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}
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}
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uint32_t AArch64SysReg::parseGenericRegister(StringRef Name) {
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// Try to parse an S<op0>_<op1>_<Cn>_<Cm>_<op2> register name
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static const Regex GenericRegPattern("^S([0-3])_([0-7])_C([0-9]|1[0-5])_C([0-9]|1[0-5])_([0-7])$");
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std::string UpperName = Name.upper();
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SmallVector<StringRef, 5> Ops;
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if (!GenericRegPattern.match(UpperName, &Ops))
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return -1;
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uint32_t Op0 = 0, Op1 = 0, CRn = 0, CRm = 0, Op2 = 0;
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uint32_t Bits;
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Ops[1].getAsInteger(10, Op0);
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Ops[2].getAsInteger(10, Op1);
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Ops[3].getAsInteger(10, CRn);
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Ops[4].getAsInteger(10, CRm);
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Ops[5].getAsInteger(10, Op2);
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Bits = (Op0 << 14) | (Op1 << 11) | (CRn << 7) | (CRm << 3) | Op2;
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return Bits;
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}
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std::string AArch64SysReg::genericRegisterString(uint32_t Bits) {
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assert(Bits < 0x10000);
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uint32_t Op0 = (Bits >> 14) & 0x3;
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uint32_t Op1 = (Bits >> 11) & 0x7;
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uint32_t CRn = (Bits >> 7) & 0xf;
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uint32_t CRm = (Bits >> 3) & 0xf;
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uint32_t Op2 = Bits & 0x7;
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return "S" + utostr(Op0) + "_" + utostr(Op1) + "_C" + utostr(CRn) + "_C" +
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utostr(CRm) + "_" + utostr(Op2);
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}
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namespace llvm {
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namespace AArch64TLBI {
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#define GET_TLBITable_IMPL
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#include "AArch64GenSystemOperands.inc"
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}
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}
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namespace llvm {
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namespace AArch64SVCR {
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#define GET_SVCR_IMPL
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#include "AArch64GenSystemOperands.inc"
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}
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}
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