cfce5b26a8
Currently the ARM backend only accpets constant expressions as the immediate operand in load and store instructions. This allows the result of symbolic expressions to be used in memory instructions. For example, 0: .space 2048 strb r2, [r0, #(.-0b)] would be assembled into the following instructions. strb r2, [r0, #2048] This only adds support to ldr, ldrb, str, and strb in arm mode to address the build failure of Linux kernel for now, but should facilitate adding support to similar instructions in the future if the need arises. Link: https://github.com/ClangBuiltLinux/linux/issues/1329 Reviewed By: peter.smith, nickdesaulniers Differential Revision: https://reviews.llvm.org/D98916
125 lines
4.1 KiB
C++
125 lines
4.1 KiB
C++
//===-- ARMFixupKinds.h - ARM Specific Fixup Entries ------------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_ARM_MCTARGETDESC_ARMFIXUPKINDS_H
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#define LLVM_LIB_TARGET_ARM_MCTARGETDESC_ARMFIXUPKINDS_H
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#include "llvm/MC/MCFixup.h"
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namespace llvm {
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namespace ARM {
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enum Fixups {
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// 12-bit PC relative relocation for symbol addresses
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fixup_arm_ldst_pcrel_12 = FirstTargetFixupKind,
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// Equivalent to fixup_arm_ldst_pcrel_12, with the 16-bit halfwords reordered.
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fixup_t2_ldst_pcrel_12,
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// 10-bit PC relative relocation for symbol addresses used in
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// LDRD/LDRH/LDRB/etc. instructions. All bits are encoded.
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fixup_arm_pcrel_10_unscaled,
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// 10-bit PC relative relocation for symbol addresses used in VFP instructions
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// where the lower 2 bits are not encoded (so it's encoded as an 8-bit
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// immediate).
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fixup_arm_pcrel_10,
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// Equivalent to fixup_arm_pcrel_10, accounting for the short-swapped encoding
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// of Thumb2 instructions.
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fixup_t2_pcrel_10,
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// 9-bit PC relative relocation for symbol addresses used in VFP instructions
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// where bit 0 not encoded (so it's encoded as an 8-bit immediate).
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fixup_arm_pcrel_9,
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// Equivalent to fixup_arm_pcrel_9, accounting for the short-swapped encoding
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// of Thumb2 instructions.
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fixup_t2_pcrel_9,
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// 12-bit immediate value.
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fixup_arm_ldst_abs_12,
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// 10-bit PC relative relocation for symbol addresses where the lower 2 bits
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// are not encoded (so it's encoded as an 8-bit immediate).
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fixup_thumb_adr_pcrel_10,
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// 12-bit PC relative relocation for the ADR instruction.
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fixup_arm_adr_pcrel_12,
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// 12-bit PC relative relocation for the ADR instruction.
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fixup_t2_adr_pcrel_12,
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// 24-bit PC relative relocation for conditional branch instructions.
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fixup_arm_condbranch,
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// 24-bit PC relative relocation for branch instructions. (unconditional)
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fixup_arm_uncondbranch,
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// 20-bit PC relative relocation for Thumb2 direct uconditional branch
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// instructions.
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fixup_t2_condbranch,
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// 20-bit PC relative relocation for Thumb2 direct branch unconditional branch
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// instructions.
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fixup_t2_uncondbranch,
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// 12-bit fixup for Thumb B instructions.
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fixup_arm_thumb_br,
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// The following fixups handle the ARM BL instructions. These can be
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// conditionalised; however, the ARM ELF ABI requires a different relocation
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// in that case: R_ARM_JUMP24 instead of R_ARM_CALL. The difference is that
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// R_ARM_CALL is allowed to change the instruction to a BLX inline, which has
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// no conditional version; R_ARM_JUMP24 would have to insert a veneer.
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//
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// MachO does not draw a distinction between the two cases, so it will treat
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// fixup_arm_uncondbl and fixup_arm_condbl as identical fixups.
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// Fixup for unconditional ARM BL instructions.
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fixup_arm_uncondbl,
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// Fixup for ARM BL instructions with nontrivial conditionalisation.
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fixup_arm_condbl,
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// Fixup for ARM BLX instructions.
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fixup_arm_blx,
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// Fixup for Thumb BL instructions.
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fixup_arm_thumb_bl,
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// Fixup for Thumb BLX instructions.
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fixup_arm_thumb_blx,
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// Fixup for Thumb branch instructions.
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fixup_arm_thumb_cb,
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// Fixup for Thumb load/store from constant pool instrs.
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fixup_arm_thumb_cp,
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// Fixup for Thumb conditional branching instructions.
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fixup_arm_thumb_bcc,
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// The next two are for the movt/movw pair
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// the 16bit imm field are split into imm{15-12} and imm{11-0}
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fixup_arm_movt_hi16, // :upper16:
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fixup_arm_movw_lo16, // :lower16:
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fixup_t2_movt_hi16, // :upper16:
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fixup_t2_movw_lo16, // :lower16:
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// Fixup for mod_imm
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fixup_arm_mod_imm,
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// Fixup for Thumb2 8-bit rotated operand
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fixup_t2_so_imm,
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// Fixups for Branch Future.
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fixup_bf_branch,
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fixup_bf_target,
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fixup_bfl_target,
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fixup_bfc_target,
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fixup_bfcsel_else_target,
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fixup_wls,
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fixup_le,
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// Marker
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LastTargetFixupKind,
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NumTargetFixupKinds = LastTargetFixupKind - FirstTargetFixupKind
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};
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}
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} // namespace llvm
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#endif
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