11074bfffe
There are a couple of bugs with the sc, scs, ll, lld instructions expanding:
1. On R6 these instruction pack immediate offset into a 9-bit field. Now
if an immediate exceeds 9-bits assembler does not perform expansion and
just rejects such instruction.
2. On 64-bit non-PIC code if an operand is a symbol assembler generates
incorrect sequence of instructions. It uses R_MIPS_HI16 and R_MIPS_LO16
relocations and skips R_MIPS_HIGHEST and R_MIPS_HIGHER ones.
To solve these problems this patch:
- Introduces `mem_simm9_exp` to mark 9-bit memory immediate operands
which require expansion. Probably later all `mem_simm9` operands will be
able to migrate on `mem_simm9_exp` and we rename it to `mem_simm9`.
- Adds new `OPERAND_MEM_SIMM9` operand type and assigns it to the
`mem_simm9_exp`. That allows to know operand size in the `processInstruction`
method and decide whether we need to expand instruction.
- Adds `expandMem9Inst` method to expand instructions with 9-bit memory
immediate operand. This method just load immediate into a "base"
register used by origibal instruction:
sc $2, 256($sp) => addiu $1, $sp, 256
sc $2, 0($1)
- Fix `expandMem16Inst` to support a correct set of relocations for
symbol loading in case of 64-bit non-PIC code.
ll $12, symbol => lui $12, 0
R_MIPS_HIGHEST symbol
daddiu $12, $12, 0
R_MIPS_HIGHER symbol
dsll $12, $12, 16
daddiu $12, $12, 0
R_MIPS_HI16 symbol
dsll $12, $12, 16
ll $12, 0($12)
R_MIPS_LO16 symbol
- Fix `expandMem16Inst` to unify handling of 3 and 4 operands
instructions.
- Delete unused now `MipsTargetStreamer::emitSCWithSymOffset` method.
Task for next patches - implement expanding for other instructions use
`mem_simm9` operand and other `mem_simm##` operands.
Differential Revision: https://reviews.llvm.org/D70648
141 lines
4.5 KiB
C++
141 lines
4.5 KiB
C++
//===-- MipsBaseInfo.h - Top level definitions for MIPS MC ------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains small standalone helper functions and enum definitions for
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// the Mips target useful for the compiler back-end and the MC libraries.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_MIPS_MCTARGETDESC_MIPSBASEINFO_H
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#define LLVM_LIB_TARGET_MIPS_MCTARGETDESC_MIPSBASEINFO_H
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#include "MipsFixupKinds.h"
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#include "MipsMCTargetDesc.h"
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#include "llvm/MC/MCExpr.h"
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#include "llvm/MC/MCInstrDesc.h"
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#include "llvm/Support/DataTypes.h"
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#include "llvm/Support/ErrorHandling.h"
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namespace llvm {
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/// MipsII - This namespace holds all of the target specific flags that
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/// instruction info tracks.
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///
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namespace MipsII {
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/// Target Operand Flag enum.
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enum TOF {
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//===------------------------------------------------------------------===//
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// Mips Specific MachineOperand flags.
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MO_NO_FLAG,
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/// MO_GOT - Represents the offset into the global offset table at which
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/// the address the relocation entry symbol resides during execution.
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MO_GOT,
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/// MO_GOT_CALL - Represents the offset into the global offset table at
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/// which the address of a call site relocation entry symbol resides
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/// during execution. This is different from the above since this flag
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/// can only be present in call instructions.
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MO_GOT_CALL,
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/// MO_GPREL - Represents the offset from the current gp value to be used
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/// for the relocatable object file being produced.
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MO_GPREL,
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/// MO_ABS_HI/LO - Represents the hi or low part of an absolute symbol
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/// address.
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MO_ABS_HI,
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MO_ABS_LO,
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/// MO_TLSGD - Represents the offset into the global offset table at which
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// the module ID and TSL block offset reside during execution (General
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// Dynamic TLS).
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MO_TLSGD,
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/// MO_TLSLDM - Represents the offset into the global offset table at which
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// the module ID and TSL block offset reside during execution (Local
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// Dynamic TLS).
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MO_TLSLDM,
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MO_DTPREL_HI,
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MO_DTPREL_LO,
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/// MO_GOTTPREL - Represents the offset from the thread pointer (Initial
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// Exec TLS).
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MO_GOTTPREL,
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/// MO_TPREL_HI/LO - Represents the hi and low part of the offset from
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// the thread pointer (Local Exec TLS).
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MO_TPREL_HI,
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MO_TPREL_LO,
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// N32/64 Flags.
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MO_GPOFF_HI,
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MO_GPOFF_LO,
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MO_GOT_DISP,
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MO_GOT_PAGE,
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MO_GOT_OFST,
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/// MO_HIGHER/HIGHEST - Represents the highest or higher half word of a
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/// 64-bit symbol address.
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MO_HIGHER,
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MO_HIGHEST,
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/// MO_GOT_HI16/LO16, MO_CALL_HI16/LO16 - Relocations used for large GOTs.
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MO_GOT_HI16,
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MO_GOT_LO16,
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MO_CALL_HI16,
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MO_CALL_LO16,
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/// Helper operand used to generate R_MIPS_JALR
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MO_JALR
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};
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enum {
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//===------------------------------------------------------------------===//
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// Instruction encodings. These are the standard/most common forms for
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// Mips instructions.
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//
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// Pseudo - This represents an instruction that is a pseudo instruction
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// or one that has not been implemented yet. It is illegal to code generate
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// it, but tolerated for intermediate implementation stages.
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Pseudo = 0,
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/// FrmR - This form is for instructions of the format R.
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FrmR = 1,
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/// FrmI - This form is for instructions of the format I.
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FrmI = 2,
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/// FrmJ - This form is for instructions of the format J.
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FrmJ = 3,
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/// FrmFR - This form is for instructions of the format FR.
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FrmFR = 4,
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/// FrmFI - This form is for instructions of the format FI.
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FrmFI = 5,
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/// FrmOther - This form is for instructions that have no specific format.
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FrmOther = 6,
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FormMask = 15,
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/// IsCTI - Instruction is a Control Transfer Instruction.
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IsCTI = 1 << 4,
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/// HasForbiddenSlot - Instruction has a forbidden slot.
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HasForbiddenSlot = 1 << 5,
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/// HasFCCRegOperand - Instruction uses an $fcc<x> register.
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HasFCCRegOperand = 1 << 6
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};
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enum OperandType : unsigned {
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OPERAND_FIRST_MIPS_MEM_IMM = MCOI::OPERAND_FIRST_TARGET,
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OPERAND_MEM_SIMM9 = OPERAND_FIRST_MIPS_MEM_IMM,
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OPERAND_LAST_MIPS_MEM_IMM = OPERAND_MEM_SIMM9
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};
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}
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}
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#endif
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