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llvm-project/llvm/lib/Target/RISCV
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Craig Topper 36d8316cc8 [RISCV] Reduce duplicate code for calling SimplifyDemandedBits. 
This encapsulates the APInt creation and worklist management into
a helper function.

To keep one common interface I've use Log2_32 in places that
previously created a mask by subtracting 1 from a power of 2.

Differential Revision: https://reviews.llvm.org/D108324
2021-08-19 07:09:38 -07:00
..
AsmParser
[RISCV] Move the $rs operand of PseudoStore from outs to ins. NFC
2021-08-08 15:58:24 -07:00
Disassembler
…
MCTargetDesc
[RISCV] Remove the _COMMUTABLE and _TA versions of FMA and wide FMA vector instructions.
2021-08-04 10:39:50 -07:00
TargetInfo
…
CMakeLists.txt
[RISCV] Add a vsetvli insert pass that can be extended to be aware of incoming VL/VTYPE from other basic blocks.
2021-05-24 11:47:27 -07:00
RISCV.h
[RISCV] Add a vsetvli insert pass that can be extended to be aware of incoming VL/VTYPE from other basic blocks.
2021-05-24 11:47:27 -07:00
RISCV.td
…
RISCVAsmPrinter.cpp
[RISCV][NFC] Don't need to create a new STI in RISCVAsmPrinter.
2021-05-10 09:33:23 +08:00
RISCVCallingConv.td
…
RISCVCallLowering.cpp
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RISCVCallLowering.h
…
RISCVExpandAtomicPseudoInsts.cpp
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RISCVExpandPseudoInsts.cpp
[RISCV] Add a vsetvli insert pass that can be extended to be aware of incoming VL/VTYPE from other basic blocks.
2021-05-24 11:47:27 -07:00
RISCVFrameLowering.cpp
[RISCV] Add FrameSetup/FrameDestroy flag to prologue/epilog instructions.
2021-07-23 11:35:19 +08:00
RISCVFrameLowering.h
[RISCV] Add FrameSetup/FrameDestroy flag to prologue/epilog instructions.
2021-07-23 11:35:19 +08:00
RISCVInsertVSETVLI.cpp
[RISCV] Teach vsetvli insertion pass that it doesn't need to insert vsetvli for unit-stride or strided loads/stores in some cases.
2021-08-12 10:05:27 -07:00
RISCVInstrFormats.td
[RISCV] Move the $rs operand of PseudoStore from outs to ins. NFC
2021-08-08 15:58:24 -07:00
RISCVInstrFormatsC.td
…
RISCVInstrFormatsV.td
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RISCVInstrInfo.cpp
[RISCV] Introduce a RISCV CondCode enum instead of using ISD:SET* in MIR. NFC
2021-08-08 17:25:37 -07:00
RISCVInstrInfo.h
[RISCV] Introduce a RISCV CondCode enum instead of using ISD:SET* in MIR. NFC
2021-08-08 17:25:37 -07:00
RISCVInstrInfo.td
[RISCV] Remove sext_inreg+add/sub/mul/shl isel patterns.
2021-08-18 11:07:11 -07:00
RISCVInstrInfoA.td
…
RISCVInstrInfoB.td
Optimize mul in the zba extension with SH*ADD
2021-07-30 08:36:28 +08:00
RISCVInstrInfoC.td
…
RISCVInstrInfoD.td
[RISCV] Support FP_TO_S/UINT_SAT for i32 and i64.
2021-08-07 16:06:00 -07:00
RISCVInstrInfoF.td
[RISCV] Support FP_TO_S/UINT_SAT for i32 and i64.
2021-08-07 16:06:00 -07:00
RISCVInstrInfoM.td
[RISCV] Remove sext_inreg+add/sub/mul/shl isel patterns.
2021-08-18 11:07:11 -07:00
RISCVInstrInfoV.td
[RISCV] Add scheduling resources for V
2021-08-03 15:47:51 -05:00
RISCVInstrInfoVPseudos.td
[RISCV] Remove the _COMMUTABLE and _TA versions of FMA and wide FMA vector instructions.
2021-08-04 10:39:50 -07:00
RISCVInstrInfoVSDPatterns.td
[RISCV] Remove the _COMMUTABLE and _TA versions of FMA and wide FMA vector instructions.
2021-08-04 10:39:50 -07:00
RISCVInstrInfoVVLPatterns.td
[RISCV] Improve codegen for shuffles with LHS/RHS splats
2021-08-09 10:31:40 +01:00
RISCVInstrInfoZfh.td
[RISCV] Support FP_TO_S/UINT_SAT for i32 and i64.
2021-08-07 16:06:00 -07:00
RISCVInstructionSelector.cpp
…
RISCVISelDAGToDAG.cpp
[RISCV] Remove sext_inreg+add/sub/mul/shl isel patterns.
2021-08-18 11:07:11 -07:00
RISCVISelDAGToDAG.h
[RISCV] Remove sext_inreg+add/sub/mul/shl isel patterns.
2021-08-18 11:07:11 -07:00
RISCVISelLowering.cpp
[RISCV] Reduce duplicate code for calling SimplifyDemandedBits.
2021-08-19 07:09:38 -07:00
RISCVISelLowering.h
[RISCV] Support FP_TO_S/UINT_SAT for i32 and i64.
2021-08-07 16:06:00 -07:00
RISCVLegalizerInfo.cpp
[globalisel][legalizer] Separate the deprecated LegalizerInfo from the current one
2021-06-01 13:23:48 -07:00
RISCVLegalizerInfo.h
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RISCVMachineFunctionInfo.h
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RISCVMCInstLower.cpp
[RISCV] Remove the _COMMUTABLE and _TA versions of FMA and wide FMA vector instructions.
2021-08-04 10:39:50 -07:00
RISCVMergeBaseOffset.cpp
[RISCV] Indicate that RISCVMergeBaseOffsetOpt preserves the CFG.
2021-08-03 08:32:36 -07:00
RISCVRegisterBankInfo.cpp
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RISCVRegisterBankInfo.h
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RISCVRegisterBanks.td
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RISCVRegisterInfo.cpp
[RISCV] Reserve an emergency spill slot for any RVV spills
2021-06-03 10:44:34 +01:00
RISCVRegisterInfo.h
…
RISCVRegisterInfo.td
[RISCV] Make VLEN no greater than 65536
2021-07-17 12:47:46 +08:00
RISCVSchedRocket.td
[RISCV] Add scheduling resources for V
2021-08-03 15:47:51 -05:00
RISCVSchedSiFive7.td
[RISCV] Add scheduling resources for V
2021-08-03 15:47:51 -05:00
RISCVSchedule.td
[RISCV] Add scheduling resources for V
2021-08-03 15:47:51 -05:00
RISCVScheduleB.td
…
RISCVScheduleV.td
[RISCV] Add scheduling resources for V
2021-08-03 15:47:51 -05:00
RISCVSubtarget.cpp
[RISCV] Make VLEN no greater than 65536
2021-07-17 12:47:46 +08:00
RISCVSubtarget.h
[RISCV] Don't enable loop vectorizer interleaving if the V extension isn't enabled.
2021-06-07 10:20:59 -07:00
RISCVSystemOperands.td
RISCV: add a few deprecated aliases for CSRs
2021-05-21 13:52:58 -07:00
RISCVTargetMachine.cpp
[RISCV] Add a vsetvli insert pass that can be extended to be aware of incoming VL/VTYPE from other basic blocks.
2021-05-24 11:47:27 -07:00
RISCVTargetMachine.h
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RISCVTargetObjectFile.cpp
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RISCVTargetObjectFile.h
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RISCVTargetTransformInfo.cpp
[RISCV] Add zext.h/zext.w to RISCVTTIImpl::getIntImmCostInst.
2021-08-18 09:40:40 -07:00
RISCVTargetTransformInfo.h
[RISCV] Use RISCV::RVVBitsPerBlock for RGK_ScalableVector in getRegisterBitWidth.
2021-08-17 11:13:15 -07:00