c2f819af73
This makes it possible for targets to define their own MCObjectFileInfo. This MCObjectFileInfo is then used to determine things like section alignment. This is a follow up to D101462 and prepares for the RISCV backend defining the text section alignment depending on the enabled extensions. Reviewed By: MaskRay Differential Revision: https://reviews.llvm.org/D101921
83 lines
3.4 KiB
C++
83 lines
3.4 KiB
C++
//===-- LlvmState.cpp -------------------------------------------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#include "LlvmState.h"
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#include "Target.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/MC/MCCodeEmitter.h"
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#include "llvm/MC/MCContext.h"
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#include "llvm/MC/MCFixup.h"
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#include "llvm/MC/MCObjectFileInfo.h"
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#include "llvm/Support/Host.h"
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#include "llvm/Support/TargetRegistry.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetOptions.h"
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namespace llvm {
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namespace exegesis {
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LLVMState::LLVMState(const std::string &Triple, const std::string &CpuName,
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const std::string &Features) {
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std::string Error;
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const Target *const TheTarget = TargetRegistry::lookupTarget(Triple, Error);
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assert(TheTarget && "unknown target for host");
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const TargetOptions Options;
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TheTargetMachine.reset(
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static_cast<LLVMTargetMachine *>(TheTarget->createTargetMachine(
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Triple, CpuName, Features, Options, Reloc::Model::Static)));
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assert(TheTargetMachine && "unable to create target machine");
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TheExegesisTarget = ExegesisTarget::lookup(TheTargetMachine->getTargetTriple());
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if (!TheExegesisTarget) {
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errs() << "no exegesis target for " << Triple << ", using default\n";
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TheExegesisTarget = &ExegesisTarget::getDefault();
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}
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PfmCounters = &TheExegesisTarget->getPfmCounters(CpuName);
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BitVector ReservedRegs = getFunctionReservedRegs(getTargetMachine());
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for (const unsigned Reg : TheExegesisTarget->getUnavailableRegisters())
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ReservedRegs.set(Reg);
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RATC.reset(
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new RegisterAliasingTrackerCache(getRegInfo(), std::move(ReservedRegs)));
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IC.reset(new InstructionsCache(getInstrInfo(), getRATC()));
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}
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LLVMState::LLVMState(const std::string &CpuName)
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: LLVMState(sys::getProcessTriple(),
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CpuName.empty() ? sys::getHostCPUName().str() : CpuName, "") {}
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std::unique_ptr<LLVMTargetMachine> LLVMState::createTargetMachine() const {
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return std::unique_ptr<LLVMTargetMachine>(static_cast<LLVMTargetMachine *>(
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TheTargetMachine->getTarget().createTargetMachine(
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TheTargetMachine->getTargetTriple().normalize(),
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TheTargetMachine->getTargetCPU(),
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TheTargetMachine->getTargetFeatureString(), TheTargetMachine->Options,
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Reloc::Model::Static)));
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}
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bool LLVMState::canAssemble(const MCInst &Inst) const {
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MCContext Context(TheTargetMachine->getTargetTriple(),
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TheTargetMachine->getMCAsmInfo(),
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TheTargetMachine->getMCRegisterInfo(),
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TheTargetMachine->getMCSubtargetInfo());
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std::unique_ptr<const MCCodeEmitter> CodeEmitter(
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TheTargetMachine->getTarget().createMCCodeEmitter(
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*TheTargetMachine->getMCInstrInfo(), *TheTargetMachine->getMCRegisterInfo(),
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Context));
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assert(CodeEmitter && "unable to create code emitter");
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SmallVector<char, 16> Tmp;
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raw_svector_ostream OS(Tmp);
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SmallVector<MCFixup, 4> Fixups;
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CodeEmitter->encodeInstruction(Inst, OS, Fixups,
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*TheTargetMachine->getMCSubtargetInfo());
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return Tmp.size() > 0;
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}
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} // namespace exegesis
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} // namespace llvm
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