Pengcheng Wang 95e38baf24

[RISCV] Enable prefetching writes (#130561) ...

We should prefetch writes since `Zicbop` has `prefetch.w`.

2025-03-11 11:39:21 +08:00

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Analysis

[AArch64][CostModel] Alter sdiv/srem cost where the divisor is constant (#123552)

2025-03-09 22:26:39 -07:00

Assembler

[RISCV][VLS] Support RISCV VLS calling convention (#100346)

2025-03-03 12:39:35 +08:00

Bindings

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Bitcode

[RISCV][VLS] Support RISCV VLS calling convention (#100346)

2025-03-03 12:39:35 +08:00

BugPoint

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CodeGen

[RISCV] Convert vsub.vx to vadd.vi if possible (#130669)

2025-03-10 16:20:14 -07:00

DebugInfo

Two fixes for DISubrangeType (#130345)

2025-03-07 14:23:05 -08:00

Demangle

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Examples

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ExecutionEngine

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Feature

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FileCheck

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Frontend/HLSL

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Instrumentation

[msan] Apply handleVectorReduceIntrinsic to max/min vector instructions (#129819)

2025-03-08 19:31:48 -08:00

Integer

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JitListener

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Linker

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LTO

[LTO] Override TargetABI from module flags if present when creating TargetMachine (#126497)

2025-03-07 14:09:26 +08:00

MachineVerifier

AMDGPU: Add pseudoinstruction for agpr or vgpr constants (#130042)

2025-03-07 09:18:22 +07:00

MC

[AMDGPU] Add GFX12 S_ALLOC_VGPR instruction (#130018)

2025-03-10 05:07:56 +01:00

Object

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ObjectYAML

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Other

Optionally print !prof metadata inline (#130303)

2025-03-07 12:22:13 -08:00

SafepointIRVerifier

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Support

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SymbolRewriter

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TableGen

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ThinLTO

[ctxprof] Prepare profile format for flat profiles (#129626)

2025-03-05 07:22:35 -08:00

tools

[MCA] Adding missing instructions in AArch64 Neoverse V1 tests (#128892)

2025-03-10 09:48:47 +00:00

Transforms

[RISCV] Enable prefetching writes (#130561)

2025-03-11 11:39:21 +08:00

Unit

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Verifier

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YAMLParser

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.clang-format

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CMakeLists.txt

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lit.cfg.py

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lit.site.cfg.py.in

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TestRunner.sh

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