f423f5627c
Summary: This concludes the patch series to eliminate StringRef forms of GNU triples from the internals of LLVM that began in r239036. At this point, the StringRef-form of GNU Triples should only be used in the public API (including IR serialization) and a couple objects that directly interact with the API (most notably the Module class). The next step is to replace these Triple objects with the TargetTuple object that will represent our authoratative/unambiguous internal equivalent to GNU Triples. Reviewers: rengolin Subscribers: llvm-commits, jholewinski, ted, rengolin Differential Revision: http://reviews.llvm.org/D10962 llvm-svn: 241472
253 lines
9.3 KiB
C++
253 lines
9.3 KiB
C++
//===-- SystemZMCTargetDesc.cpp - SystemZ target descriptions -------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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#include "SystemZMCTargetDesc.h"
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#include "InstPrinter/SystemZInstPrinter.h"
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#include "SystemZMCAsmInfo.h"
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#include "llvm/MC/MCCodeGenInfo.h"
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#include "llvm/MC/MCInstrInfo.h"
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#include "llvm/MC/MCRegisterInfo.h"
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#include "llvm/MC/MCStreamer.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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#include "llvm/Support/TargetRegistry.h"
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using namespace llvm;
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#define GET_INSTRINFO_MC_DESC
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#include "SystemZGenInstrInfo.inc"
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#define GET_SUBTARGETINFO_MC_DESC
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#include "SystemZGenSubtargetInfo.inc"
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#define GET_REGINFO_MC_DESC
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#include "SystemZGenRegisterInfo.inc"
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const unsigned SystemZMC::GR32Regs[16] = {
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SystemZ::R0L, SystemZ::R1L, SystemZ::R2L, SystemZ::R3L,
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SystemZ::R4L, SystemZ::R5L, SystemZ::R6L, SystemZ::R7L,
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SystemZ::R8L, SystemZ::R9L, SystemZ::R10L, SystemZ::R11L,
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SystemZ::R12L, SystemZ::R13L, SystemZ::R14L, SystemZ::R15L
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};
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const unsigned SystemZMC::GRH32Regs[16] = {
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SystemZ::R0H, SystemZ::R1H, SystemZ::R2H, SystemZ::R3H,
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SystemZ::R4H, SystemZ::R5H, SystemZ::R6H, SystemZ::R7H,
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SystemZ::R8H, SystemZ::R9H, SystemZ::R10H, SystemZ::R11H,
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SystemZ::R12H, SystemZ::R13H, SystemZ::R14H, SystemZ::R15H
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};
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const unsigned SystemZMC::GR64Regs[16] = {
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SystemZ::R0D, SystemZ::R1D, SystemZ::R2D, SystemZ::R3D,
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SystemZ::R4D, SystemZ::R5D, SystemZ::R6D, SystemZ::R7D,
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SystemZ::R8D, SystemZ::R9D, SystemZ::R10D, SystemZ::R11D,
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SystemZ::R12D, SystemZ::R13D, SystemZ::R14D, SystemZ::R15D
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};
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const unsigned SystemZMC::GR128Regs[16] = {
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SystemZ::R0Q, 0, SystemZ::R2Q, 0,
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SystemZ::R4Q, 0, SystemZ::R6Q, 0,
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SystemZ::R8Q, 0, SystemZ::R10Q, 0,
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SystemZ::R12Q, 0, SystemZ::R14Q, 0
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};
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const unsigned SystemZMC::FP32Regs[16] = {
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SystemZ::F0S, SystemZ::F1S, SystemZ::F2S, SystemZ::F3S,
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SystemZ::F4S, SystemZ::F5S, SystemZ::F6S, SystemZ::F7S,
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SystemZ::F8S, SystemZ::F9S, SystemZ::F10S, SystemZ::F11S,
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SystemZ::F12S, SystemZ::F13S, SystemZ::F14S, SystemZ::F15S
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};
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const unsigned SystemZMC::FP64Regs[16] = {
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SystemZ::F0D, SystemZ::F1D, SystemZ::F2D, SystemZ::F3D,
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SystemZ::F4D, SystemZ::F5D, SystemZ::F6D, SystemZ::F7D,
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SystemZ::F8D, SystemZ::F9D, SystemZ::F10D, SystemZ::F11D,
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SystemZ::F12D, SystemZ::F13D, SystemZ::F14D, SystemZ::F15D
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};
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const unsigned SystemZMC::FP128Regs[16] = {
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SystemZ::F0Q, SystemZ::F1Q, 0, 0,
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SystemZ::F4Q, SystemZ::F5Q, 0, 0,
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SystemZ::F8Q, SystemZ::F9Q, 0, 0,
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SystemZ::F12Q, SystemZ::F13Q, 0, 0
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};
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const unsigned SystemZMC::VR32Regs[32] = {
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SystemZ::F0S, SystemZ::F1S, SystemZ::F2S, SystemZ::F3S,
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SystemZ::F4S, SystemZ::F5S, SystemZ::F6S, SystemZ::F7S,
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SystemZ::F8S, SystemZ::F9S, SystemZ::F10S, SystemZ::F11S,
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SystemZ::F12S, SystemZ::F13S, SystemZ::F14S, SystemZ::F15S,
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SystemZ::F16S, SystemZ::F17S, SystemZ::F18S, SystemZ::F19S,
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SystemZ::F20S, SystemZ::F21S, SystemZ::F22S, SystemZ::F23S,
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SystemZ::F24S, SystemZ::F25S, SystemZ::F26S, SystemZ::F27S,
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SystemZ::F28S, SystemZ::F29S, SystemZ::F30S, SystemZ::F31S
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};
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const unsigned SystemZMC::VR64Regs[32] = {
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SystemZ::F0D, SystemZ::F1D, SystemZ::F2D, SystemZ::F3D,
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SystemZ::F4D, SystemZ::F5D, SystemZ::F6D, SystemZ::F7D,
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SystemZ::F8D, SystemZ::F9D, SystemZ::F10D, SystemZ::F11D,
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SystemZ::F12D, SystemZ::F13D, SystemZ::F14D, SystemZ::F15D,
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SystemZ::F16D, SystemZ::F17D, SystemZ::F18D, SystemZ::F19D,
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SystemZ::F20D, SystemZ::F21D, SystemZ::F22D, SystemZ::F23D,
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SystemZ::F24D, SystemZ::F25D, SystemZ::F26D, SystemZ::F27D,
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SystemZ::F28D, SystemZ::F29D, SystemZ::F30D, SystemZ::F31D
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};
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const unsigned SystemZMC::VR128Regs[32] = {
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SystemZ::V0, SystemZ::V1, SystemZ::V2, SystemZ::V3,
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SystemZ::V4, SystemZ::V5, SystemZ::V6, SystemZ::V7,
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SystemZ::V8, SystemZ::V9, SystemZ::V10, SystemZ::V11,
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SystemZ::V12, SystemZ::V13, SystemZ::V14, SystemZ::V15,
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SystemZ::V16, SystemZ::V17, SystemZ::V18, SystemZ::V19,
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SystemZ::V20, SystemZ::V21, SystemZ::V22, SystemZ::V23,
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SystemZ::V24, SystemZ::V25, SystemZ::V26, SystemZ::V27,
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SystemZ::V28, SystemZ::V29, SystemZ::V30, SystemZ::V31
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};
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unsigned SystemZMC::getFirstReg(unsigned Reg) {
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static unsigned Map[SystemZ::NUM_TARGET_REGS];
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static bool Initialized = false;
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if (!Initialized) {
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for (unsigned I = 0; I < 16; ++I) {
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Map[GR32Regs[I]] = I;
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Map[GRH32Regs[I]] = I;
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Map[GR64Regs[I]] = I;
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Map[GR128Regs[I]] = I;
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Map[FP128Regs[I]] = I;
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}
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for (unsigned I = 0; I < 32; ++I) {
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Map[VR32Regs[I]] = I;
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Map[VR64Regs[I]] = I;
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Map[VR128Regs[I]] = I;
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}
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}
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assert(Reg < SystemZ::NUM_TARGET_REGS);
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return Map[Reg];
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}
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static MCAsmInfo *createSystemZMCAsmInfo(const MCRegisterInfo &MRI,
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const Triple &TT) {
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MCAsmInfo *MAI = new SystemZMCAsmInfo(TT);
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MCCFIInstruction Inst =
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MCCFIInstruction::createDefCfa(nullptr,
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MRI.getDwarfRegNum(SystemZ::R15D, true),
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SystemZMC::CFAOffsetFromInitialSP);
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MAI->addInitialFrameState(Inst);
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return MAI;
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}
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static MCInstrInfo *createSystemZMCInstrInfo() {
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MCInstrInfo *X = new MCInstrInfo();
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InitSystemZMCInstrInfo(X);
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return X;
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}
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static MCRegisterInfo *createSystemZMCRegisterInfo(const Triple &TT) {
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MCRegisterInfo *X = new MCRegisterInfo();
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InitSystemZMCRegisterInfo(X, SystemZ::R14D);
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return X;
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}
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static MCSubtargetInfo *
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createSystemZMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) {
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MCSubtargetInfo *X = new MCSubtargetInfo();
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InitSystemZMCSubtargetInfo(X, TT, CPU, FS);
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return X;
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}
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static MCCodeGenInfo *createSystemZMCCodeGenInfo(const Triple &TT,
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Reloc::Model RM,
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CodeModel::Model CM,
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CodeGenOpt::Level OL) {
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MCCodeGenInfo *X = new MCCodeGenInfo();
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// Static code is suitable for use in a dynamic executable; there is no
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// separate DynamicNoPIC model.
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if (RM == Reloc::Default || RM == Reloc::DynamicNoPIC)
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RM = Reloc::Static;
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// For SystemZ we define the models as follows:
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//
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// Small: BRASL can call any function and will use a stub if necessary.
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// Locally-binding symbols will always be in range of LARL.
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//
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// Medium: BRASL can call any function and will use a stub if necessary.
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// GOT slots and locally-defined text will always be in range
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// of LARL, but other symbols might not be.
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//
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// Large: Equivalent to Medium for now.
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//
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// Kernel: Equivalent to Medium for now.
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//
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// This means that any PIC module smaller than 4GB meets the
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// requirements of Small, so Small seems like the best default there.
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//
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// All symbols bind locally in a non-PIC module, so the choice is less
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// obvious. There are two cases:
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//
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// - When creating an executable, PLTs and copy relocations allow
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// us to treat external symbols as part of the executable.
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// Any executable smaller than 4GB meets the requirements of Small,
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// so that seems like the best default.
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//
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// - When creating JIT code, stubs will be in range of BRASL if the
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// image is less than 4GB in size. GOT entries will likewise be
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// in range of LARL. However, the JIT environment has no equivalent
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// of copy relocs, so locally-binding data symbols might not be in
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// the range of LARL. We need the Medium model in that case.
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if (CM == CodeModel::Default)
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CM = CodeModel::Small;
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else if (CM == CodeModel::JITDefault)
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CM = RM == Reloc::PIC_ ? CodeModel::Small : CodeModel::Medium;
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X->initMCCodeGenInfo(RM, CM, OL);
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return X;
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}
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static MCInstPrinter *createSystemZMCInstPrinter(const Triple &T,
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unsigned SyntaxVariant,
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const MCAsmInfo &MAI,
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const MCInstrInfo &MII,
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const MCRegisterInfo &MRI) {
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return new SystemZInstPrinter(MAI, MII, MRI);
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}
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extern "C" void LLVMInitializeSystemZTargetMC() {
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// Register the MCAsmInfo.
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TargetRegistry::RegisterMCAsmInfo(TheSystemZTarget,
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createSystemZMCAsmInfo);
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// Register the MCCodeGenInfo.
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TargetRegistry::RegisterMCCodeGenInfo(TheSystemZTarget,
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createSystemZMCCodeGenInfo);
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// Register the MCCodeEmitter.
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TargetRegistry::RegisterMCCodeEmitter(TheSystemZTarget,
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createSystemZMCCodeEmitter);
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// Register the MCInstrInfo.
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TargetRegistry::RegisterMCInstrInfo(TheSystemZTarget,
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createSystemZMCInstrInfo);
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// Register the MCRegisterInfo.
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TargetRegistry::RegisterMCRegInfo(TheSystemZTarget,
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createSystemZMCRegisterInfo);
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// Register the MCSubtargetInfo.
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TargetRegistry::RegisterMCSubtargetInfo(TheSystemZTarget,
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createSystemZMCSubtargetInfo);
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// Register the MCAsmBackend.
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TargetRegistry::RegisterMCAsmBackend(TheSystemZTarget,
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createSystemZMCAsmBackend);
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// Register the MCInstPrinter.
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TargetRegistry::RegisterMCInstPrinter(TheSystemZTarget,
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createSystemZMCInstPrinter);
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}
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