03855df197
Summary: * Add 64-bit address space feature. * Rename SIMD feature to SIMD128. * Handle single-thread model with an IR pass (same way ARM does). * Rename generic processor to MVP, to follow design's lead. * Add bleeding-edge processors, with all features included. * Fix a few DEBUG_TYPE to match other backends. Test Plan: ninja check Reviewers: sunfish Subscribers: jfb, llvm-commits Differential Revision: http://reviews.llvm.org/D10880 llvm-svn: 241211
47 lines
1.5 KiB
TableGen
47 lines
1.5 KiB
TableGen
// WebAssemblyInstrAtomics.td-WebAssembly Atomic codegen support-*- tablegen -*-
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// WebAssembly Atomic operand code-gen constructs.
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//
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//===----------------------------------------------------------------------===//
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// TODO: Implement atomic instructions.
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//===----------------------------------------------------------------------===//
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// Atomic fences
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//===----------------------------------------------------------------------===//
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// TODO: add atomic fences here...
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//===----------------------------------------------------------------------===//
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// Atomic loads
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//===----------------------------------------------------------------------===//
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// TODO: add atomic loads here...
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//===----------------------------------------------------------------------===//
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// Atomic stores
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//===----------------------------------------------------------------------===//
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// TODO: add atomic stores here...
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//===----------------------------------------------------------------------===//
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// Low-level exclusive operations
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//===----------------------------------------------------------------------===//
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// TODO: add exclusive operations here...
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// Load-exclusives.
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// Store-exclusives.
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// Store-release-exclusives.
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// And clear exclusive.
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