vangthao95 9708da6f2d

AMDGPU/GlobalISel: RegBankLegalize rules for fmad_ftz (#188132)

2026-03-24 08:08:23 -07:00

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AArch64

[TargetLowering] In expandDIVREMByConstant, combine shift by trailing zeros with chunk shifts. (#188086)

2026-03-24 07:57:58 -07:00

AMDGPU

AMDGPU/GlobalISel: RegBankLegalize rules for fmad_ftz (#188132)

2026-03-24 08:08:23 -07:00

ARC

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ARM

[DAG] ComputeKnownBits - set low bit to zero for ADD(X,X) (#186461)

2026-03-23 16:10:36 +00:00

AVR

[AVR] Improve expansion of pseudo instruction SPREAD (#186780)

2026-03-16 21:24:20 +01:00

BPF

[BPF] Use ".L" local prefix label for basic blocks (#95103)

2026-03-15 19:28:00 +01:00

CSKY

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DirectX

[HLSL] Add WaveActiveBitAnd builtin function (#187149)

2026-03-23 10:19:18 -07:00

Generic

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Hexagon

[Hexagon] Optimize load/store instruction during widening (#186962)

2026-03-24 11:41:24 +05:30

Inputs

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Lanai

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LoongArch

[LoongArch] Mark VREPLGR2VR/XVREPLGR2VR as rematerializable to reduce register pressure (#187431)

2026-03-23 21:40:41 +08:00

M68k

[M68k] Fix pipeline.ll test after CodeGenPrepare analysis change (#187617)

2026-03-20 09:57:45 +08:00

Mips

[Mips] Add r5900 (PlayStation 2 Emotion Engine) FPU Support (#178942)

2026-03-22 23:48:00 -04:00

MIR

[GlobalISel][LLT] Introduce FPInfo for LLT (Enable bfloat, ppc128float and others in GlobalISel) (#155107)

2026-03-24 08:40:39 -04:00

MIR2Vec

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MLRegAlloc

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MSP430

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NVPTX

[NVPTX] Print param space sub-qualifiers where supported (#187350)

2026-03-20 20:44:56 -07:00

PowerPC

[DAG] ComputeKnownBits - set low bit to zero for ADD(X,X) (#186461)

2026-03-23 16:10:36 +00:00

RISCV

[TargetLowering] In expandDIVREMByConstant, combine shift by trailing zeros with chunk shifts. (#188086)

2026-03-24 07:57:58 -07:00

SPARC

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SPIRV

[SPIRV] Fix OpBuildNDRange (#186153)

2026-03-23 19:11:04 +01:00

SystemZ

[SystemZ] Remove custom lowering of f16 IS_FPCLASS (#187532)

2026-03-22 17:19:24 +01:00

Thumb

[ARM] Try to lower sign bit SELECT_CC to shift (#186349)

2026-03-16 09:32:43 +01:00

Thumb2

[DAGCombine] Optimize away cond ? 1 : 0 post-legalization (#186771)

2026-03-20 16:23:18 +01:00

VE

[LegalizeTypes] Keep non-negative info in SUB(CTLZ) (#186338)

2026-03-24 09:17:17 +01:00

WebAssembly

[WebAssembly][FastISel] Fold i64 extension chains into widened loads (#187934)

2026-03-24 12:56:06 +09:00

WinCFGuard

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WinEH

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X86

[X86] getFauxShuffleMask - decode insert_subvector(undef, x, c) as shuffle if c != 0 (#188258)

2026-03-24 14:58:57 +00:00

XCore

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Xtensa

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