Simon Pilgrim 449e3fad62

[X86] combineConcatVectorOps - add concatenation handling for X86ISD::VSHLD/VSHRD funnel shift nodes (#132915) ...

Concat the nodes if we can merge either of the operands for free.

2025-03-25 13:23:47 +00:00

..

AArch64

[AArch64][SME2] Don't preserve ZT0 around SME ABI routines (#132722)

2025-03-25 10:09:25 +00:00

AMDGPU

[AMDGPU][NPM] Port SIInsertHardClauses to NPM (#130062)

2025-03-25 15:33:32 +05:30

ARC

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ARM

[CodeGen][NPM] Port LiveDebugValues to NPM (#131563)

2025-03-24 11:34:45 +05:30

AVR

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BPF

[BPF] Fix BitCast Assertion with NonZero AddrSpace (#130722)

2025-03-11 11:23:53 -07:00

CSKY

[CSKY] Update fp16-promote.ll test (NFC)

2025-03-05 12:42:32 +01:00

DirectX

[HLSL] Add support to branch/flatten attributes to switch (#131739)

2025-03-24 16:17:19 -07:00

Generic

[RemoveDIs] Remove "try-debuginfo-iterators..." test flags (#130298)

2025-03-14 15:50:49 +00:00

Hexagon

[hexagon] Bump the default version to v68 (#132304)

2025-03-21 20:08:45 -05:00

Inputs

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Lanai

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LoongArch

[LoongArch] Pre-commit tests for vector shift (#132702)

2025-03-25 10:31:54 +08:00

M68k

Rename ExpandLargeFpConvertPass to ExpandFpPass (#131128)

2025-03-14 13:11:45 +01:00

Mips

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MIR

[AMDGPU] Allocate scratch space for dVGPRs for CWSR (#130055)

2025-03-19 13:49:19 +01:00

MLRegAlloc

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MSP430

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NVPTX

[NVPTX] Auto-Upgrade !"align" metadata on return values to stackalign (#131726)

2025-03-24 12:00:44 -07:00

PowerPC

[shrinkwrap] PowerPC's FP register should be honored when processing the save point for prologue. (#129855)

2025-03-21 12:55:39 -04:00

RISCV

[RISCV][test] Add a test for vector hasAndNot

2025-03-24 17:54:18 +01:00

SPARC

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SPIRV

[HLSL] Add support to branch/flatten attributes to switch (#131739)

2025-03-24 16:17:19 -07:00

SystemZ

[MC][SystemZ] Introduce Target Specific HLASM Streamer for z/OS (#130535)

2025-03-21 11:36:35 -04:00

Thumb

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Thumb2

[CodeGen] Combine two loops in SlotIndexes.cpp file (#127631)

2025-03-07 08:17:23 +07:00

VE

[NVPTX] Legalize ctpop and ctlz in operation legalization (#130668)

2025-03-12 09:28:40 -07:00

WebAssembly

[WebAssembly] Lower wide SIMD i8 muls (#130785)

2025-03-21 06:57:57 +00:00

WinCFGuard

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WinEH

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X86

[X86] combineConcatVectorOps - add concatenation handling for X86ISD::VSHLD/VSHRD funnel shift nodes (#132915)

2025-03-25 13:23:47 +00:00

XCore

Reland: [MC] output inlined-at debug info (#106230) (#130306)

2025-03-11 09:43:14 -04:00

Xtensa

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