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llvm-project/llvm/test/CodeGen/RISCV
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Daniel Sanders a16bd4f9f2 [RISCV GlobalISel] Adding initial GlobalISel infrastructure 
Summary:
Add an initial GlobalISel skeleton for RISCV. It can only run ir translator for `ret void`.

Patch by Andrew Wei

Reviewers: asb, sabuasal, apazos, lenary, simoncook, lewis-revill, edward-jones, rogfer01, xiangzhai, rovka, Petar.Avramovic, mgorny, dsanders

Reviewed By: dsanders

Subscribers: pzheng, s.egerton, dsanders, hiraditya, rbar, johnrusso, niosHD, kito-cheng, shiva0217, jrtc27, MaskRay, zzheng, MartinMosbeck, brucehoult, the_o, PkmX, jocewei, psnobl, benna, Jim, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D65219

llvm-svn: 369467
2019-08-20 22:53:24 +00:00
..
GlobalISel
[RISCV GlobalISel] Adding initial GlobalISel infrastructure
2019-08-20 22:53:24 +00:00
add-before-shl.ll
[RISCV] Fix ICE in isDesirableToCommuteWithShift
2019-08-12 13:51:00 +00:00
addc-adde-sube-subc.ll
[RISCV][NFC] Add nounwind attribute to functions missing it in test/CodeGen/RISCV
2019-05-23 12:43:13 +00:00
addcarry.ll
[RISCV][NFC] Add nounwind attribute to functions missing it in test/CodeGen/RISCV
2019-05-23 12:43:13 +00:00
align.ll
…
alloca.ll
…
alu8.ll
…
alu16.ll
…
alu32.ll
[RISCV] Custom legalize i32 operations for RV64 to reduce signed extensions
2019-08-06 00:24:00 +00:00
alu64.ll
[RISCV][NFC] Add nounwind attribute to functions missing it in test/CodeGen/RISCV
2019-05-23 12:43:13 +00:00
analyze-branch.ll
…
arith-with-overflow.ll
…
atomic-cmpxchg-flag.ll
[RISCV][NFC] Add nounwind attribute to functions missing it in test/CodeGen/RISCV
2019-05-23 12:43:13 +00:00
atomic-cmpxchg.ll
[RISCV][NFC] Add nounwind attribute to functions missing it in test/CodeGen/RISCV
2019-05-16 13:56:23 +00:00
atomic-fence.ll
…
atomic-load-store.ll
…
atomic-rmw.ll
Revert r368339 "[MBP] Disable aggressive loop rotate in plain mode"
2019-08-12 14:23:13 +00:00
bare-select.ll
[RISCV][NFC] Add nounwind attribute to functions missing it in test/CodeGen/RISCV
2019-05-23 12:43:13 +00:00
blockaddress.ll
…
branch-relaxation.ll
[RISCV] Match GNU tools canonical JALR and add aliases
2019-07-16 04:56:43 +00:00
branch.ll
[RISCV][NFC] Add nounwind attribute to functions missing it in test/CodeGen/RISCV
2019-05-23 12:43:13 +00:00
bswap-ctlz-cttz-ctpop.ll
[RISCV] Only mark fp as reserved if the function has a dedicated frame pointer
2019-03-13 16:33:45 +00:00
byval.ll
…
callee-saved-fpr32s.ll
[RISCV][NFC] Add nounwind attribute to functions missing it in test/CodeGen/RISCV
2019-05-16 13:56:23 +00:00
callee-saved-fpr64s.ll
[RISCV][NFC] Add nounwind attribute to functions missing it in test/CodeGen/RISCV
2019-05-16 13:56:23 +00:00
callee-saved-gprs.ll
[RISCV][NFC] Add nounwind attribute to functions missing it in test/CodeGen/RISCV
2019-05-16 13:56:23 +00:00
calling-conv-ilp32-ilp32f-common.ll
[RISCV] Add codegen support for ilp32f, ilp32d, lp64f, and lp64d ("hard float") ABIs
2019-03-30 17:59:30 +00:00
calling-conv-ilp32-ilp32f-ilp32d-common.ll
[RISCV] Add codegen support for ilp32f, ilp32d, lp64f, and lp64d ("hard float") ABIs
2019-03-30 17:59:30 +00:00
calling-conv-ilp32.ll
[RISCV] Only mark fp as reserved if the function has a dedicated frame pointer
2019-03-13 16:33:45 +00:00
calling-conv-ilp32d.ll
[RISCV] Add codegen support for ilp32f, ilp32d, lp64f, and lp64d ("hard float") ABIs
2019-03-30 17:59:30 +00:00
calling-conv-ilp32f-ilp32d-common.ll
[RISCV] Add codegen support for ilp32f, ilp32d, lp64f, and lp64d ("hard float") ABIs
2019-03-30 17:59:30 +00:00
calling-conv-lp64-lp64f-common.ll
[RISCV] Add codegen support for ilp32f, ilp32d, lp64f, and lp64d ("hard float") ABIs
2019-03-30 17:59:30 +00:00
calling-conv-lp64-lp64f-lp64d-common.ll
[RISCV] Custom legalize i32 operations for RV64 to reduce signed extensions
2019-08-06 00:24:00 +00:00
calling-conv-lp64.ll
[RISCV] Only mark fp as reserved if the function has a dedicated frame pointer
2019-03-13 16:33:45 +00:00
calling-conv-rv32f-ilp32.ll
…
calling-conv-sext-zext.ll
…
calls.ll
[RISCV] Lower calls through PLT
2019-06-18 14:29:45 +00:00
codemodel-lowering.ll
[RISCV] Implement adding a displacement to a BlockAddress
2019-04-05 08:40:57 +00:00
compress-inline-asm.ll
…
compress.ll
…
disable-tail-calls.ll
…
div.ll
…
double-arith.ll
…
double-bitmanip-dagcombines.ll
…
double-br-fcmp.ll
[RISCV] Add seto pattern expansion
2019-04-01 09:54:14 +00:00
double-calling-conv.ll
[RISCV] Add DAGCombine for (SplitF64 (ConstantFP x))
2019-03-30 09:15:47 +00:00
double-convert.ll
…
double-fcmp.ll
[RISCV] Add seto pattern expansion
2019-04-01 09:54:14 +00:00
double-frem.ll
…
double-imm.ll
[RISCV] Add DAGCombine for (SplitF64 (ConstantFP x))
2019-03-30 09:15:47 +00:00
double-intrinsics.ll
[RISCV] Only mark fp as reserved if the function has a dedicated frame pointer
2019-03-13 16:33:45 +00:00
double-mem.ll
[RISCV] Only mark fp as reserved if the function has a dedicated frame pointer
2019-03-13 16:33:45 +00:00
double-previous-failure.ll
[RISCV] Add DAGCombine for (SplitF64 (ConstantFP x))
2019-03-30 09:15:47 +00:00
double-select-fcmp.ll
[RISCV] Add seto pattern expansion
2019-04-01 09:54:14 +00:00
double-stack-spill-restore.ll
…
dwarf-eh.ll
[RISCV][NFC] Remove outdated TODO from test/CodeGen/RISCV/dwarf-eh.ll
2019-07-17 14:04:48 +00:00
exception-pointer-register.ll
[RISCV] Specify registers used in DWARF exception handling
2019-07-08 09:16:47 +00:00
fixups-diff.ll
…
fixups-relax-diff.ll
[DebugInfo] Generate fixups as emitting DWARF .debug_frame/.eh_frame.
2019-07-19 02:03:34 +00:00
float-arith.ll
…
float-bit-preserving-dagcombines.ll
[RISCV] Support Bit-Preserving FP in F/D Extensions
2019-06-07 12:20:14 +00:00
float-bitmanip-dagcombines.ll
…
float-br-fcmp.ll
[RISCV] Add seto pattern expansion
2019-04-01 09:54:14 +00:00
float-convert.ll
…
float-fcmp.ll
[RISCV] Add seto pattern expansion
2019-04-01 09:54:14 +00:00
float-frem.ll
…
float-imm.ll
…
float-intrinsics.ll
[RISCV] Only mark fp as reserved if the function has a dedicated frame pointer
2019-03-13 16:33:45 +00:00
float-mem.ll
[RISCV] Only mark fp as reserved if the function has a dedicated frame pointer
2019-03-13 16:33:45 +00:00
float-select-fcmp.ll
[RISCV] Add seto pattern expansion
2019-04-01 09:54:14 +00:00
flt-rounds.ll
…
fp128.ll
…
frame-info.ll
[RISCV] Add CFI directives for RISCV prologue/epilog.
2019-06-12 03:04:22 +00:00
frame.ll
…
frameaddr-returnaddr.ll
…
get-setcc-result-type.ll
[RISCV][NFC] Add nounwind attribute to functions missing it in test/CodeGen/RISCV
2019-05-23 12:43:13 +00:00
hoist-global-addr-base.ll
[RISCV][NFC] Add nounwind attribute to functions missing it in test/CodeGen/RISCV
2019-05-23 12:43:13 +00:00
i32-icmp.ll
[RISCV] Improve codegen for icmp {ne,eq} with a constant
2019-03-26 12:55:00 +00:00
imm-cse.ll
[RISCV] Add RISCV-specific TargetTransformInfo
2019-06-21 13:36:09 +00:00
imm.ll
…
indirectbr.ll
[RISCV] Match GNU tools canonical JALR and add aliases
2019-07-16 04:56:43 +00:00
init-array.ll
[IR] Disallow llvm.global_ctors and llvm.global_dtors of the 2-field form in textual format
2019-05-15 02:35:32 +00:00
inline-asm-abi-names.ll
[RISCV] Allow ABI Names in Inline Assembly Constraints
2019-08-08 14:59:16 +00:00
inline-asm-clobbers.ll
[RISCV] Add support for lowering floating point inlineasm clobbers
2019-07-31 09:07:21 +00:00
inline-asm-d-abi-names.ll
[RISCV] Allow ABI Names in Inline Assembly Constraints
2019-08-08 14:59:16 +00:00
inline-asm-d-constraint-f.ll
[RISCV] Allow ABI Names in Inline Assembly Constraints
2019-08-08 14:59:16 +00:00
inline-asm-f-abi-names.ll
[RISCV] Allow ABI Names in Inline Assembly Constraints
2019-08-08 14:59:16 +00:00
inline-asm-f-constraint-f.ll
[RISCV] Allow ABI Names in Inline Assembly Constraints
2019-08-08 14:59:16 +00:00
inline-asm-i-constraint-i1.ll
[TargetLowering] Extend bool args to inline-asm according to getBooleanType
2019-05-22 16:16:15 +00:00
inline-asm-invalid.ll
Emit diagnostic if an inline asm constraint requires an immediate
2019-08-03 05:52:47 +00:00
inline-asm.ll
[RISCV] Lower inline asm constraint A for RISC-V
2019-08-16 10:28:34 +00:00
interrupt-attr-args-error.ll
…
interrupt-attr-invalid.ll
…
interrupt-attr-nocall.ll
[RISCV][NFC] Add nounwind attribute to functions missing it in test/CodeGen/RISCV
2019-05-16 13:56:23 +00:00
interrupt-attr-ret-error.ll
…
interrupt-attr.ll
[RISCV][NFC] Add nounwind attribute to functions missing it in test/CodeGen/RISCV
2019-05-16 13:56:23 +00:00
jumptable.ll
[RISCV][NFC] Add nounwind attribute to functions missing it in test/CodeGen/RISCV
2019-05-23 12:43:13 +00:00
large-stack.ll
[RISCV] Only mark fp as reserved if the function has a dedicated frame pointer
2019-03-13 16:33:45 +00:00
legalize-fneg.ll
[RISCV][NFC] Add nounwind attribute to functions missing it in test/CodeGen/RISCV
2019-05-23 12:43:13 +00:00
lit.local.cfg
…
lsr-legaladdimm.ll
…
mattr-invalid-combination.ll
[RISCV] Add basic RV32E definitions and MC layer support
2019-03-22 11:21:40 +00:00
mem64.ll
…
mem.ll
…
mul.ll
…
musttail-call.ll
…
option-norelax.ll
…
option-norvc.ll
…
option-relax.ll
…
option-rvc.ll
[RISCV] Match GNU tools canonical JALR and add aliases
2019-07-16 04:56:43 +00:00
pic-models.ll
[RISCV] Add lowering of addressing sequences for PIC
2019-06-11 12:57:47 +00:00
pr40333.ll
…
prefetch.ll
…
readcyclecounter.ll
[RISCV] Support @llvm.readcyclecounter() Intrinsic
2019-07-05 12:35:21 +00:00
rem.ll
…
remat.ll
Revert r368339 "[MBP] Disable aggressive loop rotate in plain mode"
2019-08-12 14:23:13 +00:00
rotl-rotr.ll
[RISCV][NFC] Add nounwind attribute to functions missing it in test/CodeGen/RISCV
2019-05-23 12:43:13 +00:00
rv32e.ll
[RISCV] Add basic RV32E definitions and MC layer support
2019-03-22 11:21:40 +00:00
rv32i-rv64i-float-double.ll
[RISCV] Only mark fp as reserved if the function has a dedicated frame pointer
2019-03-13 16:33:45 +00:00
rv64d-double-convert.ll
…
rv64f-float-convert.ll
…
rv64i-exhaustive-w-insts.ll
[RISCV] Custom legalize i32 operations for RV64 to reduce signed extensions
2019-08-06 00:24:00 +00:00
rv64i-tricky-shifts.ll
[RISCV][NFC] Add nounwind attribute to functions missing it in test/CodeGen/RISCV
2019-05-23 12:43:13 +00:00
rv64i-w-insts-legalization.ll
[RISCV] Custom legalize i32 operations for RV64 to reduce signed extensions
2019-08-06 00:24:00 +00:00
rv64m-exhaustive-w-insts.ll
[RISCV] Custom legalize i32 operations for RV64 to reduce signed extensions
2019-08-06 00:24:00 +00:00
rv64m-w-insts-legalization.ll
[RISCV] Custom legalize i32 operations for RV64 to reduce signed extensions
2019-08-06 00:24:00 +00:00
sdata-limit-0.ll
[RISCV] Put data smaller than eight bytes to small data section
2019-04-11 04:59:13 +00:00
sdata-limit-4.ll
[RISCV] Put data smaller than eight bytes to small data section
2019-04-11 04:59:13 +00:00
sdata-limit-8.ll
[RISCV] Put data smaller than eight bytes to small data section
2019-04-11 04:59:13 +00:00
sdata-local-sym.ll
[RISCV] Put data smaller than eight bytes to small data section
2019-04-11 04:59:13 +00:00
select-cc.ll
[RISCV][NFC] Add nounwind attribute to functions missing it in test/CodeGen/RISCV
2019-05-23 12:43:13 +00:00
select-optimize-multiple.ll
[RISCV] Custom legalize i32 operations for RV64 to reduce signed extensions
2019-08-06 00:24:00 +00:00
select-optimize-multiple.mir
[RISCV] Fix test after r363757
2019-06-19 03:18:48 +00:00
setcc-logic.ll
[RISCV] Update setcc-logic.ll codegen test
2019-03-26 15:41:45 +00:00
sext-zext-trunc.ll
[RISCV][NFC] Add nounwind attribute to functions missing it in test/CodeGen/RISCV
2019-05-23 12:43:13 +00:00
shift-masked-shamt.ll
…
shifts.ll
[RISCV] Custom lower SHL_PARTS, SRA_PARTS, SRL_PARTS
2019-04-16 14:38:32 +00:00
split-offsets.ll
[DAGCombiner] [CodeGenPrepare] More comprehensive GEP splitting
2019-06-17 10:54:12 +00:00
stack-realignment-unsupported.ll
[RISCV] Minimal stack realignment support
2019-08-08 14:40:54 +00:00
stack-realignment.ll
[RISCV] Minimal stack realignment support
2019-08-08 14:40:54 +00:00
tail-calls.ll
[RISCV][NFC] Add nounwind attribute to functions missing it in test/CodeGen/RISCV
2019-05-23 12:43:13 +00:00
target-abi-invalid.ll
[RISCV] Support -target-abi at the MC layer and for codegen
2019-03-09 09:28:06 +00:00
target-abi-valid.ll
[RISCV] Add codegen support for ilp32f, ilp32d, lp64f, and lp64d ("hard float") ABIs
2019-03-30 17:59:30 +00:00
tls-models.ll
[RISCV] Add lowering of global TLS addresses
2019-06-19 08:40:59 +00:00
umulo-128-legalisation-lowering.ll
[RISCV][NFC] Add nounwind attribute to functions missing it in test/CodeGen/RISCV
2019-05-16 13:56:23 +00:00
vararg.ll
[RISCV] Custom legalize i32 operations for RV64 to reduce signed extensions
2019-08-06 00:24:00 +00:00
wide-mem.ll
…
zext-with-load-is-free.ll
[RISCV][NFC] Add nounwind attribute to functions missing it in test/CodeGen/RISCV
2019-05-23 12:43:13 +00:00