shylie/llvm-project
1
0
Fork 0
Code Issues Pull Requests Actions 6 Packages Projects Releases Wiki Activity
llvm-project/llvm/test/CodeGen
History
Matt Arsenault 9b1bcaea4e AMDGPU: Update tests for lower i1 change 
I forgot to squash the test updates for b32d3d9e81cdd9275d19cd2a396c461edc9e7189
2021-07-27 12:14:58 -04:00
..
AArch64
Revert "[GlobalISel] Add scalar widening for G_MERGE_VALUES destination"
2021-07-26 19:52:12 -07:00
AMDGPU
AMDGPU: Update tests for lower i1 change
2021-07-27 12:14:58 -04:00
ARC
…
ARM
[Local] Do not introduce a new llvm.trap before unreachable
2021-07-26 23:33:36 -05:00
AVR
[AVR] Only support sp, r0 and r1 in llvm.read_register
2021-07-24 14:03:27 +02:00
BPF
[BPF] Use elementtype attribute for preserve.array/struct.index intrinsics
2021-07-17 11:09:18 +02:00
Generic
[PowerPC] Add pwr7 and pwr10 support to IBM MASSV pass on AIX
2021-07-26 23:21:38 +00:00
Hexagon
[Local] Do not introduce a new llvm.trap before unreachable
2021-07-26 23:33:36 -05:00
Inputs
…
Lanai
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
M68k
[M68k][GloballSel] LegalizerInfo implementation
2021-07-15 13:00:43 -06:00
Mips
[llvm][sve] Lowering for VLS truncating stores
2021-07-23 14:04:55 +01:00
MIR
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
MSP430
…
NVPTX
[NVPTX] Add select(cc,binop(),binop()) fast-math tests
2021-07-18 15:30:24 +01:00
PowerPC
[PowerPC] add more testcases for ld_splat; nfc
2021-07-27 11:45:26 +00:00
RISCV
[SelectionDAG] Support scalable splats in U(ADD|SUB)SAT combines
2021-07-27 10:52:34 +01:00
SPARC
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
SystemZ
[SystemZ][z/OS] Initial code to generate assembly files on z/OS
2021-07-27 11:29:15 -04:00
Thumb
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
Thumb2
[ARM] Implement isLoad/StoreFromStackSlot for MVE stack stores accesses
2021-07-27 09:11:58 +01:00
VE
[LegalizeTypes][VE] Don't Expand BITREVERSE/BSWAP during type legalization promotion if they will be promoted for NVT in op legalization.
2021-06-29 11:00:11 -07:00
WebAssembly
[WebAssembly] Codegen for extmul SIMD instructions
2021-07-27 08:41:30 -07:00
WinCFGuard
…
WinEH
…
X86
[DebugInfo][InstrRef] Correctly update DBG_PHIs during instr scheduling
2021-07-27 15:12:46 +01:00
XCore
Update @llvm.powi to handle different int sizes for the exponent
2021-06-17 09:38:28 +02:00