10068cd654
This patch introduces per kernel environment. Previously, flags such as execution mode are set through global variables with name like `__kernel_name_exec_mode`. They are accessible on the host by reading the corresponding global variable, but not from the device. Besides, some assumptions, such as no nested parallelism, are not per kernel basis, preventing us applying per kernel optimization in the device runtime. This is a combination and refinement of patch series D116908, D116909, and D116910. Depend on D155886. Reviewed By: jdoerfert Differential Revision: https://reviews.llvm.org/D142569
115 lines
6.5 KiB
C++
115 lines
6.5 KiB
C++
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _
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// REQUIRES: amdgpu-registered-target
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// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple x86_64-unknown-unknown -fopenmp-targets=amdgcn-amd-amdhsa -emit-llvm-bc %s -o %t-ppc-host.bc
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// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple amdgcn-amd-amdhsa -fopenmp-targets=amdgcn-amd-amdhsa -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s
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// expected-no-diagnostics
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#ifndef HEADER
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#define HEADER
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#define N 1000
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int test_amdgcn_target_tid_threads() {
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int arr[N];
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#pragma omp target
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for (int i = 0; i < N; i++) {
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arr[i] = 1;
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}
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return arr[0];
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}
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int test_amdgcn_target_tid_threads_simd() {
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int arr[N];
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#pragma omp target simd
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for (int i = 0; i < N; i++) {
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arr[i] = 1;
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}
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return arr[0];
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}
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#endif
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// CHECK-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z30test_amdgcn_target_tid_threadsv_l14
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// CHECK-SAME: (ptr noundef nonnull align 4 dereferenceable(4000) [[ARR:%.*]]) #[[ATTR0:[0-9]+]] {
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[ARR_ADDR:%.*]] = alloca ptr, align 8, addrspace(5)
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// CHECK-NEXT: [[I:%.*]] = alloca i32, align 4, addrspace(5)
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// CHECK-NEXT: [[ARR_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[ARR_ADDR]] to ptr
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// CHECK-NEXT: [[I_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I]] to ptr
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// CHECK-NEXT: store ptr [[ARR]], ptr [[ARR_ADDR_ASCAST]], align 8
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// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[ARR_ADDR_ASCAST]], align 8
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// CHECK-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(ptr addrspacecast (ptr addrspace(1) @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z30test_amdgcn_target_tid_threadsv_l14_kernel_environment to ptr))
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// CHECK-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
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// CHECK-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
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// CHECK: user_code.entry:
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// CHECK-NEXT: store i32 0, ptr [[I_ASCAST]], align 4
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// CHECK-NEXT: br label [[FOR_COND:%.*]]
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// CHECK: for.cond:
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// CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[I_ASCAST]], align 4
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// CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP2]], 1000
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// CHECK-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
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// CHECK: for.body:
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// CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr [[I_ASCAST]], align 4
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// CHECK-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP3]] to i64
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// CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i32], ptr [[TMP0]], i64 0, i64 [[IDXPROM]]
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// CHECK-NEXT: store i32 1, ptr [[ARRAYIDX]], align 4
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// CHECK-NEXT: br label [[FOR_INC:%.*]]
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// CHECK: for.inc:
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// CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[I_ASCAST]], align 4
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// CHECK-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1
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// CHECK-NEXT: store i32 [[INC]], ptr [[I_ASCAST]], align 4
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// CHECK-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]]
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// CHECK: worker.exit:
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// CHECK-NEXT: ret void
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// CHECK: for.end:
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// CHECK-NEXT: call void @__kmpc_target_deinit()
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// CHECK-NEXT: ret void
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//
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//
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// CHECK-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z35test_amdgcn_target_tid_threads_simdv_l23
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// CHECK-SAME: (ptr noundef nonnull align 4 dereferenceable(4000) [[ARR:%.*]]) #[[ATTR1:[0-9]+]] {
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[ARR_ADDR:%.*]] = alloca ptr, align 8, addrspace(5)
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// CHECK-NEXT: [[TMP:%.*]] = alloca i32, align 4, addrspace(5)
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// CHECK-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4, addrspace(5)
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// CHECK-NEXT: [[I:%.*]] = alloca i32, align 4, addrspace(5)
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// CHECK-NEXT: [[ARR_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[ARR_ADDR]] to ptr
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// CHECK-NEXT: [[TMP_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[TMP]] to ptr
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// CHECK-NEXT: [[DOTOMP_IV_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_IV]] to ptr
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// CHECK-NEXT: [[I_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I]] to ptr
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// CHECK-NEXT: store ptr [[ARR]], ptr [[ARR_ADDR_ASCAST]], align 8
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// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[ARR_ADDR_ASCAST]], align 8
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// CHECK-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(ptr addrspacecast (ptr addrspace(1) @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z35test_amdgcn_target_tid_threads_simdv_l23_kernel_environment to ptr))
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// CHECK-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
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// CHECK-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
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// CHECK: user_code.entry:
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// CHECK-NEXT: store i32 0, ptr [[DOTOMP_IV_ASCAST]], align 4
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// CHECK-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
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// CHECK: omp.inner.for.cond:
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// CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4, !llvm.access.group [[ACC_GRP11:![0-9]+]]
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// CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP2]], 1000
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// CHECK-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
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// CHECK: omp.inner.for.body:
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// CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4, !llvm.access.group [[ACC_GRP11]]
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// CHECK-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1
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// CHECK-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
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// CHECK-NEXT: store i32 [[ADD]], ptr [[I_ASCAST]], align 4, !llvm.access.group [[ACC_GRP11]]
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// CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[I_ASCAST]], align 4, !llvm.access.group [[ACC_GRP11]]
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// CHECK-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP4]] to i64
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// CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i32], ptr [[TMP0]], i64 0, i64 [[IDXPROM]]
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// CHECK-NEXT: store i32 1, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP11]]
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// CHECK-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
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// CHECK: omp.body.continue:
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// CHECK-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
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// CHECK: omp.inner.for.inc:
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// CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4, !llvm.access.group [[ACC_GRP11]]
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// CHECK-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP5]], 1
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// CHECK-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV_ASCAST]], align 4, !llvm.access.group [[ACC_GRP11]]
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// CHECK-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]]
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// CHECK: worker.exit:
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// CHECK-NEXT: ret void
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// CHECK: omp.inner.for.end:
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// CHECK-NEXT: store i32 1000, ptr [[I_ASCAST]], align 4
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// CHECK-NEXT: call void @__kmpc_target_deinit()
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// CHECK-NEXT: ret void
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//
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