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llvm-project/llvm/lib/Target/RISCV
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Craig Topper 8677aaa1a3 [RISCV][GISel] Add initial pre-legalizer combiners copying from AArch64.
2023-09-18 10:59:00 -07:00
..
AsmParser
[MC] Change tryParseRegister to return ParseStatus (NFC)
2023-09-06 10:28:12 +03:00
Disassembler
[RISCV] Rename Ventana DecoderNamespace to XVentana for matching other extension. NFC.
2023-08-19 12:44:59 +08:00
GISel
[RISCV][GISel] Add initial pre-legalizer combiners copying from AArch64.
2023-09-18 10:59:00 -07:00
MCA
[RISCV][llvm-mca] Fix Fix getLMUL values
2023-09-05 09:34:47 -07:00
MCTargetDesc
[MC][RISCV] Add assembly syntax highlighting for RISCV (#65853)
2023-09-13 01:46:25 +08:00
TargetInfo
[RISCV] Replace RISCV -> RISC-V in comments. NFC
2023-03-27 09:50:17 -07:00
CMakeLists.txt
[RISCV][GISel] Add initial pre-legalizer combiners copying from AArch64.
2023-09-18 10:59:00 -07:00
RISCV.h
[RISCV][GISel] Add initial pre-legalizer combiners copying from AArch64.
2023-09-18 10:59:00 -07:00
RISCV.td
[RISCV] Replace RISCV -> RISC-V in comments. NFC
2023-03-27 09:50:17 -07:00
RISCVAsmPrinter.cpp
[RISCV] Only emit .option when extension is supported
2023-09-18 00:30:13 -07:00
RISCVCallingConv.td
[RISCV] Simplify the definitions of interrupt CSRs
2023-07-11 11:20:24 +08:00
RISCVCodeGenPrepare.cpp
[RISCV] Replace RISCV->RISC-V in strings.
2023-03-27 09:50:17 -07:00
RISCVCombine.td
[RISCV][GISel] Add initial pre-legalizer combiners copying from AArch64.
2023-09-18 10:59:00 -07:00
RISCVExpandAtomicPseudoInsts.cpp
[RISCV] Prevent tryToFoldBNEOnCmpXchgResult from deleting AND if it has others users.
2023-08-28 10:11:12 -07:00
RISCVExpandPseudoInsts.cpp
[RISCV][NFC] Add RISCVSubtarget field to RISCVExpandPseudo and RISCVPreRAExpandPseudo
2023-07-21 16:50:11 +01:00
RISCVFeatures.td
[RISCV] Add Zvfhmin extension support for llvm RISCV backend
2023-08-23 16:47:47 +08:00
RISCVFrameLowering.cpp
[RISCV] Adjust first sp size to use c.addi16sp.
2023-09-06 14:26:52 +08:00
RISCVFrameLowering.h
[llvm] Fix duplicate word typos. NFC
2023-09-01 18:25:16 -07:00
RISCVGatherScatterLowering.cpp
[RISCV] Match constant indices of non-index type when forming strided ops (#65777)
2023-09-18 09:41:34 -07:00
RISCVGISel.td
[RISCV][GISel] Add initial pre-legalizer combiners copying from AArch64.
2023-09-18 10:59:00 -07:00
RISCVInsertReadWriteCSR.cpp
[RISCV] Separate hasRoundModeOpNum into separate VXRM and FRM functions.
2023-08-21 10:00:23 -07:00
RISCVInsertVSETVLI.cpp
[RISCV] Optimize floating point scalar move and splat
2023-09-06 16:39:30 +08:00
RISCVInstrFormats.td
[RISCV] Add a common base class for RVInstR variations. NFC
2023-07-31 13:06:23 -07:00
RISCVInstrFormatsC.td
[RISCV] Remove unused Opcode field from RVInst16. NFC
2023-07-20 08:18:06 -07:00
RISCVInstrFormatsV.td
[RISCV] Remove Opcode field from RVInst. Assign Inst{6-0} directly. NFC
2023-07-20 08:18:06 -07:00
RISCVInstrInfo.cpp
[RISCV] Remove debug location to spill/reload instructions
2023-09-09 16:39:28 +08:00
RISCVInstrInfo.h
[RISCV] Implement KCFI operand bundle lowering
2023-06-23 22:57:56 +00:00
RISCVInstrInfo.td
[RISCV] Remove trailing whitespace. NFC.
2023-08-21 10:01:13 +08:00
RISCVInstrInfoA.td
[SDAG][RISCV] Avoid neg instructions when lowering atomic_load_sub with a constant rhs
2023-09-16 17:09:41 +08:00
RISCVInstrInfoC.td
[RISCV] Add Zce extension.
2023-07-13 12:22:06 -07:00
RISCVInstrInfoD.td
[RISCV] Add lowering for scalar fmaximum/fminimum.
2023-07-24 13:46:35 -07:00
RISCVInstrInfoF.td
[RISCV] Add lowering for scalar fmaximum/fminimum.
2023-07-24 13:46:35 -07:00
RISCVInstrInfoM.td
[NFC][RISCV] Rewrite TableGen files using named arguments
2023-07-20 17:17:49 +08:00
RISCVInstrInfoV.td
[RISCV] Add SchedRead for merge operand
2023-08-13 12:25:22 -07:00
RISCVInstrInfoVPseudos.td
[RISCV] Specify FilterClassField to filter out unneeded pseudos (#65460)
2023-09-15 13:02:26 +08:00
RISCVInstrInfoVSDPatterns.td
[RISCV] Form vmv.s.f/x from single element splats via DAG combine
2023-08-30 12:44:36 -07:00
RISCVInstrInfoVVLPatterns.td
[RISCV] Form vmv.s.f/x from single element splats via DAG combine
2023-08-30 12:44:36 -07:00
RISCVInstrInfoXCV.td
[RISCV][NFC] Rename CVROR, NFC
2023-08-20 16:36:03 +10:00
RISCVInstrInfoXSf.td
[RISCV] Simplify some XSfvcp tablegen. NFC
2023-08-11 12:01:57 -07:00
RISCVInstrInfoXTHead.td
[RISCV][NFC] Use named arguments in newly added changes
2023-08-10 17:14:13 +08:00
RISCVInstrInfoXVentana.td
[RISCV] Rename Ventana DecoderNamespace to XVentana for matching other extension. NFC.
2023-08-19 12:44:59 +08:00
RISCVInstrInfoZb.td
[RISCV] Use add.uw for (or (and X, 0xFFFFFFFF), Y) if Y has zeroes in the lower 32 bits. (#65402)
2023-09-05 21:05:53 -07:00
RISCVInstrInfoZc.td
[RISCV] Fix rlist grammar for cm.push, cm.popret, cm.popretz and cm.pop in RISCV zcmp Extension
2023-08-15 01:06:41 +08:00
RISCVInstrInfoZfa.td
[RISCV] Simplify tablegen class for Zfa FLI instructions. NFC
2023-07-25 09:33:54 -07:00
RISCVInstrInfoZfbfmin.td
[RISCV] Remove trailing whitespace from some .td files.
2023-08-11 12:29:20 -07:00
RISCVInstrInfoZfh.td
[RISCV] Add lowering for scalar fmaximum/fminimum.
2023-07-24 13:46:35 -07:00
RISCVInstrInfoZicbo.td
[SelectionDAG][RISCV][PowerPC][X86] Use TargetConstant for immediates for ISD::PREFETCH. (#66601)
2023-09-18 08:58:50 -07:00
RISCVInstrInfoZicond.td
[RISCV] Handle seteq/setne conditions for CZERO_NEZ/CZERO_EQZ during isel.
2023-07-26 10:06:08 -07:00
RISCVInstrInfoZk.td
[RISCV] Add a common base class for RVInstI variations. NFC
2023-07-31 13:03:35 -07:00
RISCVInstrInfoZvfbf.td
[RISCV] Model all 3 arithmetic sources of vector FMA at MC layer.
2023-08-04 09:08:16 -07:00
RISCVInstrInfoZvk.td
[RISCV] Bump vector crypto to v1.0 RC2
2023-08-17 21:19:59 -07:00
RISCVISelDAGToDAG.cpp
[NFC][CodeGen] Change CodeGenOpt::Level/CodeGenFileType into enum classes (#66295)
2023-09-14 14:10:14 -07:00
RISCVISelDAGToDAG.h
[NFC][CodeGen] Change CodeGenOpt::Level/CodeGenFileType into enum classes (#66295)
2023-09-14 14:10:14 -07:00
RISCVISelLowering.cpp
[RISCV] Fix crash when legalizing mgather/scatter on rv32
2023-09-18 08:36:23 -07:00
RISCVISelLowering.h
[SDAG][RISCV] Avoid expanding is-power-of-2 pattern on riscv32/64 with zbb
2023-09-17 02:56:09 +08:00
RISCVMachineFunctionInfo.cpp
[RISCV] Replace RISCV -> RISC-V in comments. NFC
2023-03-27 09:50:17 -07:00
RISCVMachineFunctionInfo.h
[RISCV] Disable zcmp push/pop for variadic functions. (#65302)
2023-09-11 13:09:01 +08:00
RISCVMacroFusion.cpp
[RISCV] Replace RISCV -> RISC-V in comments. NFC
2023-03-27 09:50:17 -07:00
RISCVMacroFusion.h
[RISCV] Replace RISCV -> RISC-V in comments. NFC
2023-03-27 09:50:17 -07:00
RISCVMakeCompressible.cpp
[RISCV] Avoid RegScavenger::forward in RISCVMakeCompressibleOpt
2023-05-16 09:10:49 +01:00
RISCVMergeBaseOffset.cpp
[RISCV] Teach RISCVMergeBaseOffset to handle BlockAddress
2023-09-18 11:47:14 +08:00
RISCVMoveMerger.cpp
[RISCV][NFC] Adjust RISCVMoveMerge.cpp header to match standard style
2023-06-27 13:35:41 +01:00
RISCVOptWInstrs.cpp
[RISCV] Add Zicond instructions to RISCVOptWInstrs like XVentanaCondOps.
2023-08-23 16:57:16 -07:00
RISCVProcessors.td
[RISCV] Add support for custom instructions for Sifive S76.
2023-06-26 11:36:00 -07:00
RISCVPushPopOptimizer.cpp
[RISCV] Add bounds check before use on returned iterator.
2023-08-14 16:06:09 -07:00
RISCVRedundantCopyElimination.cpp
[RISCV] Replace RISCV->RISC-V in strings.
2023-03-27 09:50:17 -07:00
RISCVRegisterInfo.cpp
[llvm] Remove SmallSet from MachineInstr.h
2023-08-12 18:15:27 +01:00
RISCVRegisterInfo.h
[RISCV] Replace RISCV -> RISC-V in comments. NFC
2023-03-27 09:50:17 -07:00
RISCVRegisterInfo.td
[RISCV] Remove trailing whitespace. NFC.
2023-08-21 10:01:13 +08:00
RISCVRVVInitUndef.cpp
[RISCV] Use NoReg in place of IMPLICIT_DEF for undefined passthru operands
2023-08-14 12:57:38 -07:00
RISCVSchedRocket.td
[TableGen] Rename ResourceCycles and StartAtCycle to clarify semantics
2023-08-24 19:21:36 -07:00
RISCVSchedSiFive7.td
[RISCV] Fix SiFive7 formula for Reductions and ordered Reductions (#65385)
2023-09-05 23:04:21 -04:00
RISCVSchedSyntacoreSCR1.td
[TableGen] Rename ResourceCycles and StartAtCycle to clarify semantics
2023-08-24 19:21:36 -07:00
RISCVSchedule.td
[RISCV] Remove WriteJmpReg. Use WriteJalr in its place.
2023-06-25 21:59:27 -07:00
RISCVScheduleV.td
[RISCV] Add SchedRead for Merge operands on MASK Pseudos
2023-07-26 10:57:07 -07:00
RISCVScheduleZb.td
[RISCV] Split BEXT and BEXTI Write classes. NFC.
2023-07-17 15:52:40 -07:00
RISCVSubtarget.cpp
[RISCV] Remove XLen field from RISCVSubtarget [nfc]
2023-09-01 07:42:03 -07:00
RISCVSubtarget.h
[RISCV] Remove XLen field from RISCVSubtarget [nfc]
2023-09-01 07:42:03 -07:00
RISCVSystemOperands.td
[RISCV] Add support for custom CSRs for Sifive S76.
2023-07-14 09:51:15 -07:00
RISCVTargetMachine.cpp
[RISCV][GISel] Add initial pre-legalizer combiners copying from AArch64.
2023-09-18 10:59:00 -07:00
RISCVTargetMachine.h
[NFC][CodeGen] Change CodeGenOpt::Level/CodeGenFileType into enum classes (#66295)
2023-09-14 14:10:14 -07:00
RISCVTargetObjectFile.cpp
[RISCV] RISCVELFTargetObjectFile: use 2-byte alignment for .text if RVC
2023-05-11 13:44:37 -07:00
RISCVTargetObjectFile.h
[RISCV] RISCVELFTargetObjectFile: use 2-byte alignment for .text if RVC
2023-05-11 13:44:37 -07:00
RISCVTargetTransformInfo.cpp
[RISCV] Move slide and gather costing to TLI [NFC] (PR #65396)
2023-09-07 18:28:17 -07:00
RISCVTargetTransformInfo.h
[RISCV] Move slide and gather costing to TLI [NFC] (PR #65396)
2023-09-07 18:28:17 -07:00