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llvm-project/llvm/lib/CodeGen/SelectionDAG
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Craig Topper fdfdee98ac [DAGCombiner] Teach SimplifySetCC SETUGE X, SINTMIN -> SETLT X, 0 and SETULE X, SINTMAX -> SETGT X, -1. 
These aren't the canonical forms we'd get from InstCombine, but
we do have X86 tests for them. Recognizing them is pretty cheap.

While there make use of APInt:isSignedMinValue/isSignedMaxValue
instead of creating a new APInt to compare with. Also use
SelectionDAG::getAllOnesConstant helper to hide the all ones
APInt creation.
2020-08-08 22:27:16 -07:00
..
CMakeLists.txt
[cmake] Explicitly mark libraries defined in lib/ as "Component Libraries"
2019-11-21 10:48:08 -08:00
DAGCombiner.cpp
[DAGCombiner] reassociate reciprocal sqrt expression to eliminate FP division, part 2
2020-08-08 10:38:06 -04:00
FastISel.cpp
[FastISel] Don't transform FSUB(-0, X) -> FNEG(X) in FastISel
2020-08-04 14:42:53 -05:00
FunctionLoweringInfo.cpp
[Statepoint] Consolidate relocation type tracking [NFC]
2020-07-29 11:45:31 -07:00
InstrEmitter.cpp
[Statepoints] Support lowering gc relocations to virtual registers
2020-07-25 14:26:05 -07:00
InstrEmitter.h
InstrEmitter.h - reduce SelectionDAG.h include to SelectionDAGNodes.h include.
2020-04-19 11:52:31 +01:00
LegalizeDAG.cpp
[Intrinsic] Add sshl.sat/ushl.sat, saturated shift intrinsics.
2020-08-07 15:09:24 +02:00
LegalizeFloatTypes.cpp
[FPEnv] Intrinsic llvm.roundeven
2020-05-26 19:24:58 +07:00
LegalizeIntegerTypes.cpp
[Intrinsic] Add sshl.sat/ushl.sat, saturated shift intrinsics.
2020-08-07 15:09:24 +02:00
LegalizeTypes.cpp
[CodeGen] Replace calls to getVectorNumElements() in DAGTypeLegalizer::SetSplitVector
2020-07-10 08:29:17 +01:00
LegalizeTypes.h
[Intrinsic] Add sshl.sat/ushl.sat, saturated shift intrinsics.
2020-08-07 15:09:24 +02:00
LegalizeTypesGeneric.cpp
[LegalTypes] Move VSELECT node creation out of WidenVSELECTAndMask and push to 2 of the 3 callers.
2020-08-06 13:18:16 -07:00
LegalizeVectorOps.cpp
[Intrinsic] Add sshl.sat/ushl.sat, saturated shift intrinsics.
2020-08-07 15:09:24 +02:00
LegalizeVectorTypes.cpp
[Intrinsic] Add sshl.sat/ushl.sat, saturated shift intrinsics.
2020-08-07 15:09:24 +02:00
LLVMBuild.txt
Update the file headers across all of the LLVM projects in the monorepo
2019-01-19 08:50:56 +00:00
ResourcePriorityQueue.cpp
ResourcePriorityQueue.h - reduce unnecessary includes to forward declarations. NFC.
2020-05-26 19:22:14 +01:00
ScheduleDAGFast.cpp
DAG: Use Register
2020-04-08 13:44:31 -04:00
ScheduleDAGRRList.cpp
[ScheduleDAGRRList] Pacify overload mismatch in std::min.
2020-07-23 11:56:50 +01:00
ScheduleDAGSDNodes.cpp
[Statepoints] Support lowering gc relocations to virtual registers
2020-07-25 14:26:05 -07:00
ScheduleDAGSDNodes.h
DAG: Use Register
2020-04-08 13:44:31 -04:00
ScheduleDAGVLIW.cpp
Prune Analysis includes from SelectionDAG.h
2019-10-19 01:07:48 +00:00
SDNodeDbgValue.h
Update the file headers across all of the LLVM projects in the monorepo
2019-01-19 08:50:56 +00:00
SelectionDAG.cpp
[DAG] GetDemandedBits - remove custom AND handling.
2020-08-07 12:55:47 +01:00
SelectionDAGAddressAnalysis.cpp
Prune a LegacyDivergenceAnalysis and MachineLoopInfo include each
2019-10-19 01:31:09 +00:00
SelectionDAGBuilder.cpp
[Intrinsic] Add sshl.sat/ushl.sat, saturated shift intrinsics.
2020-08-07 15:09:24 +02:00
SelectionDAGBuilder.h
[FPEnv] Don't transform FSUB(-0,X)->FNEG(X) in SelectionDAGBuilder.
2020-08-03 10:22:25 -05:00
SelectionDAGDumper.cpp
[Intrinsic] Add sshl.sat/ushl.sat, saturated shift intrinsics.
2020-08-07 15:09:24 +02:00
SelectionDAGISel.cpp
DAG: Remove redundant finalizeLowering call
2020-07-08 18:48:20 -04:00
SelectionDAGPrinter.cpp
Utility to dump .dot representation of SelectionDAG without firing viewer
2020-06-04 11:51:48 +05:30
SelectionDAGTargetInfo.cpp
Update the file headers across all of the LLVM projects in the monorepo
2019-01-19 08:50:56 +00:00
StatepointLowering.cpp
[Statepoint] Enable cross block relocates w/vreg lowering
2020-07-29 13:32:51 -07:00
StatepointLowering.h
[Statepoint] Consolidate relocation type tracking [NFC]
2020-07-29 11:45:31 -07:00
TargetLowering.cpp
[DAGCombiner] Teach SimplifySetCC SETUGE X, SINTMIN -> SETLT X, 0 and SETULE X, SINTMAX -> SETGT X, -1.
2020-08-08 22:27:16 -07:00