yingopq 9cc7ee16e3
[Mips] Support llvm.readcyclecounter intrinsic (#114953)
The llvm.readcyclecounter intrinsic can be implemented via the `rdhwr
$3, $hwr_cc` instruction.
$hwr_cc: High-resolution cycle counter. This register provides read
access to the coprocessor 0 Count Register.

Fix #106318.
2025-02-11 08:47:50 +08:00
..