Matt Arsenault db024764c1

AMDGPU: Fix not diagnosing unaligned VGPRs for vsrc operands (#155104) ...

This was not checking the alignment requirement for 64-bit
operands which accept inline immediates. Not all custom operand
types were handled in the switch, so round out with explicit
handling of all enum values, and change the default to use
the default checks for unhandled cases.

Fixes #155095

2025-08-25 17:42:58 +09:00

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av_mov_b64_imm_pseudo.mir

AMDGPU: Add pseudoinstruction for 64-bit agpr or vgpr constants (#154499)

2025-08-20 22:54:37 +09:00

fix-illegal-vector-copies.mir

[AMDGPU,test] Change llc -march= to -mtriple=

2024-12-15 10:54:21 -08:00

issue98474-missing-def-liveout-physical-subregister.mir

VirtRegRewriter: Add implicit register defs for live out undef lanes (#112679)

2024-10-28 17:33:53 -07:00

lit.local.cfg

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register-killed-inside-loop.mir

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test_g_bitcast.mir

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test_g_incompatible_range.mir

MachineVerifier: Fix check for range type (#124894)

2025-01-30 10:56:12 +07:00

test_g_intrinsic_w_side_effects.mir

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test_g_intrinsic.mir

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undef-should-only-be-set-on-subreg-defs.mir

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undef-virt-reg-entry-block.mir

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undef-virt-reg-nonentry-block.mir

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unsupported-subreg-index-aligned-vgpr-check.mir

MachineVerifier: Print name of failing subregister index (#129491)

2025-03-04 11:25:34 +07:00

unsupported-unaligned-vgpr-check-vsrc-operand.mir

AMDGPU: Fix not diagnosing unaligned VGPRs for vsrc operands (#155104)

2025-08-25 17:42:58 +09:00

verifier-ec-subreg-liveness.mir

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verifier-implicit-virtreg-invalid-physreg-liveness.mir

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verifier-pseudo-terminators.mir

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verifier-sdwa-selection.mir

[AMDGPU] Verify SdwaSel value range (#128898)

2025-02-27 08:11:29 +01:00

verify-av-mov-imm-pseudo.mir

AMDGPU: Add pseudoinstruction for agpr or vgpr constants (#130042)

2025-03-07 09:18:22 +07:00

verify-implicit-def.mir

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verify-reg-sequence.mir

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writelane_m0.mir

[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)

2025-02-13 15:17:12 +01:00