Alexey Bataev bf2f241458 [SLP]Support LShr as base for copyable elements ...

Added support for LShr instructions as base for copyable elements. Also,
added simple analysis for best base instruction selection, if multiple
candidates are available.

Fixed scheduling after cancellation

Reviewers: hiraditya, RKSimon

Reviewed By: RKSimon

Pull Request: https://github.com/llvm/llvm-project/pull/153393

2025-08-14 19:12:27 -07:00

..

32-bit.ll

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64-bit-vector.ll

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accelerate-vector-functions-inseltpoison.ll

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accelerate-vector-functions.ll

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alternate-vectorization-split-node.ll

[SLP]Support LShr as base for copyable elements

2025-08-14 19:12:27 -07:00

buildvector-reduce.ll

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buildvector-vectorize.ll

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commute.ll

[SLP]Initial FMAD support (#149102)

2025-08-11 05:53:55 -07:00

div.ll

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exp.ll

Reland [VectorUtils] Trivially vectorize ldexp, [l]lround (#152476)

2025-08-07 12:07:29 +01:00

ext-trunc.ll

[AArch64,TTI] Remove RealUse check for vector insert/extract costs. (#146526)

2025-07-15 15:19:27 +01:00

external-non-inst-use.ll

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external-use-icmp.ll

[AArch64,TTI] Remove RealUse check for vector insert/extract costs. (#146526)

2025-07-15 15:19:27 +01:00

extract-subvector-long-input.ll

[AArch64,TTI] Remove RealUse check for vector insert/extract costs. (#146526)

2025-07-15 15:19:27 +01:00

extractelements-to-shuffle.ll

[AArch64,TTI] Remove RealUse check for vector insert/extract costs. (#146526)

2025-07-15 15:19:27 +01:00

extracts-from-scalarizable-vector.ll

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fminimumnum.ll

Vectorize: Support fminimumnum and fmaximumnum (#131781)

2025-04-15 08:08:45 +08:00

fmulladd.ll

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fpsat.ll

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fround.ll

Reland [VectorUtils] Trivially vectorize ldexp, [l]lround (#152476)

2025-08-07 12:07:29 +01:00

fshl.ll

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gather-buildvector-with-minbitwidth-user.ll

[AArch64,TTI] Remove RealUse check for vector insert/extract costs. (#146526)

2025-07-15 15:19:27 +01:00

gather-cost.ll

[SLP] Drop unnecessary '' from around -passes=... arg lists to appease update_test_checks.py when run on DOS. NFC.

2025-07-10 12:18:41 +01:00

gather-load-128.ll

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gather-load-min-required-vf-2.ll

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gather-reduce.ll

[SLP] Avoid -passes=instcombine stages in SLP tests (#146257)

2025-07-02 06:14:41 -04:00

gather-root.ll

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gather-with-minbith-user.ll

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getelementptr2.ll

[AArch64,TTI] Remove RealUse check for vector insert/extract costs. (#146526)

2025-07-15 15:19:27 +01:00

getelementptr.ll

[AArch64,TTI] Remove RealUse check for vector insert/extract costs. (#146526)

2025-07-15 15:19:27 +01:00

horizontal.ll

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insertelement-inseltpoison.ll

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insertelement.ll

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InstructionsState-is-invalid-0.ll

[SLP]Remove emission of vector_insert/vector_extract intrinsics

2025-07-11 15:26:45 -04:00

invalid_type.ll

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landing_pad.ll

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lit.local.cfg

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load-store-q.ll

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loadi8.ll

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loadorder.ll

[SLP]Remove emission of vector_insert/vector_extract intrinsics

2025-07-11 15:26:45 -04:00

masked-loads-side-effects-after-vec.ll

[SLP]Cache data for compressed loads before codegen

2025-04-17 08:43:44 -07:00

matmul.ll

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memory-runtime-checks-in-loops.ll

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memory-runtime-checks.ll

[AArch64,TTI] Remove RealUse check for vector insert/extract costs. (#146526)

2025-07-15 15:19:27 +01:00

minbitwidth-cast-node-length.ll

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minimum-sizes.ll

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mismatched-intrinsics.ll

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mul.ll

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multiple_reduction.ll

[AArch64,TTI] Remove RealUse check for vector insert/extract costs. (#146526)

2025-07-15 15:19:27 +01:00

nontemporal.ll

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phi-node-bitwidt-op-not.ll

[AArch64,TTI] Remove RealUse check for vector insert/extract costs. (#146526)

2025-07-15 15:19:27 +01:00

phi-use-order-scalable.ll

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PR38339.ll

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reduce-add-i64.ll

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reduce-fadd.ll

[SLP]Remove emission of vector_insert/vector_extract intrinsics

2025-07-11 15:26:45 -04:00

reduce-maximumnum-minimumnum.ll

[IVDescriptors] Support reductions with minimumnum/maximumnum. (#137335)

2025-04-28 11:16:36 +01:00

remarks.ll

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reorder-fmuladd-crash.ll

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reordered-loads.ll

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reused-scalar-repeated-in-node.ll

[AArch64] Change the cost of fma and fmuladd to match fmul. (#152963)

2025-08-14 21:53:45 +01:00

scalable-external-user.ll

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scalable-vector.ll

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scalarization-overhead.ll

[SLP]Initial FMAD support (#149102)

2025-08-11 05:53:55 -07:00

sdiv-pow2.ll

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shuffle-vectors-mask-size.ll

[SLP]Remove emission of vector_insert/vector_extract intrinsics

2025-07-11 15:26:45 -04:00

slp-abs.ll

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slp-and-reduction.ll

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slp-fma-loss.ll

Revert "[SLP] Emit reduction instead of 2 extracts + scalar op, when vectorizing operands (#147583)"

2025-07-10 14:55:22 +01:00

slp-frem.ll

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slp-or-reduction.ll

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slp-xor-reduction.ll

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spillcost-di.ll

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spillcost-order.ll

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splat-loads.ll

[AArch64,TTI] Remove RealUse check for vector insert/extract costs. (#146526)

2025-07-15 15:19:27 +01:00

store-ptr.ll

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transpose-inseltpoison.ll

[SLP] Avoid -passes=instcombine stages in SLP tests (#146257)

2025-07-02 06:14:41 -04:00

transpose.ll

[SLP] Avoid -passes=instcombine stages in SLP tests (#146257)

2025-07-02 06:14:41 -04:00

trunc-insertion.ll

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tsc-s116.ll

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tsc-s352.ll

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unreachable-blocks-with-phis.ll

[AArch64,TTI] Remove RealUse check for vector insert/extract costs. (#146526)

2025-07-15 15:19:27 +01:00

unsigned-after-sext-node.ll

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uselistorder.ll

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user-node-not-in-bitwidths.ll

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vec3-base.ll

[SLP] Make getSameOpcode support interchangeable instructions. (#135797)

2025-04-16 00:08:59 +08:00

vec3-calls.ll

[SLP]Remove emission of vector_insert/vector_extract intrinsics

2025-07-11 15:26:45 -04:00

vec3-reorder-reshuffle.ll

[AArch64] Change the cost of fma and fmuladd to match fmul. (#152963)

2025-08-14 21:53:45 +01:00

vec15-base.ll

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vecreduceadd.ll

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vector-getelementptr.ll

[AArch64,TTI] Remove RealUse check for vector insert/extract costs. (#146526)

2025-07-15 15:19:27 +01:00

vectorizable-selects-min-max.ll

[SLP] Drop unnecessary '' from around -passes=... arg lists to appease update_test_checks.py when run on DOS. NFC.

2025-07-10 12:18:41 +01:00

vectorizable-selects-uniform-cmps.ll

[AArch64,TTI] Remove RealUse check for vector insert/extract costs. (#146526)

2025-07-15 15:19:27 +01:00

vectorize-free-extracts-inserts.ll

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widen.ll

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