5bad5d84a1
Add support for using the existing SCRATCH_STORE_BLOCK and SCRATCH_LOAD_BLOCK instructions for saving and restoring callee-saved VGPRs. This is controlled by a new subtarget feature, block-vgpr-csr. It does not include WWM registers - those will be saved and restored individually, just like before. This patch does not change the ABI. Use of this feature may lead to slightly increased stack usage, because the memory is not compacted if certain registers don't have to be transferred (this will happen in practice for calling conventions where the callee and caller saved registers are interleaved in groups of 8). However, if the registers at the end of the block of 32 don't have to be transferred, we don't need to use a whole 128-byte stack slot - we can trim some space off the end of the range. In order to implement this feature, we need to rely less on the target-independent code in the PrologEpilogInserter, so we override several new methods in SIFrameLowering. We also add new pseudos, SI_BLOCK_SPILL_V1024_SAVE/RESTORE. One peculiarity is that both the SI_BLOCK_V1024_RESTORE pseudo and the SCRATCH_LOAD_BLOCK instructions will have all the registers that are not transferred added as implicit uses. This is done in order to inform LiveRegUnits that those registers are not available before the restore (since we're not really restoring them - so we can't afford to scavenge them). Unfortunately, this trick doesn't work with the save, so before the save all the registers in the block will be unavailable (see the unit test). This was reverted due to failures in the builds with expensive checks on, now fixed by always updating LiveIntervals and SlotIndexes in SILowerSGPRSpills.
115 lines
5.0 KiB
C++
115 lines
5.0 KiB
C++
//===--------------------- SIFrameLowering.h --------------------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_AMDGPU_SIFRAMELOWERING_H
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#define LLVM_LIB_TARGET_AMDGPU_SIFRAMELOWERING_H
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#include "AMDGPUFrameLowering.h"
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#include "SIRegisterInfo.h"
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namespace llvm {
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class SIFrameLowering final : public AMDGPUFrameLowering {
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public:
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SIFrameLowering(StackDirection D, Align StackAl, int LAO,
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Align TransAl = Align(1))
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: AMDGPUFrameLowering(D, StackAl, LAO, TransAl) {}
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~SIFrameLowering() override = default;
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void emitEntryFunctionPrologue(MachineFunction &MF,
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MachineBasicBlock &MBB) const;
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void emitPrologue(MachineFunction &MF,
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MachineBasicBlock &MBB) const override;
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void emitEpilogue(MachineFunction &MF,
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MachineBasicBlock &MBB) const override;
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StackOffset getFrameIndexReference(const MachineFunction &MF, int FI,
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Register &FrameReg) const override;
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void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs,
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RegScavenger *RS = nullptr) const override;
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void determineCalleeSavesSGPR(MachineFunction &MF, BitVector &SavedRegs,
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RegScavenger *RS = nullptr) const;
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void determinePrologEpilogSGPRSaves(MachineFunction &MF, BitVector &SavedRegs,
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bool NeedExecCopyReservedReg) const;
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void emitCSRSpillStores(MachineFunction &MF, MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI, DebugLoc &DL,
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LiveRegUnits &LiveUnits, Register FrameReg,
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Register FramePtrRegScratchCopy) const;
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void emitCSRSpillRestores(MachineFunction &MF, MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI, DebugLoc &DL,
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LiveRegUnits &LiveUnits, Register FrameReg,
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Register FramePtrRegScratchCopy) const;
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bool
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assignCalleeSavedSpillSlots(MachineFunction &MF,
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const TargetRegisterInfo *TRI,
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std::vector<CalleeSavedInfo> &CSI) const override;
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bool assignCalleeSavedSpillSlots(MachineFunction &MF,
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const TargetRegisterInfo *TRI,
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std::vector<CalleeSavedInfo> &CSI,
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unsigned &MinCSFrameIndex,
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unsigned &MaxCSFrameIndex) const override;
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bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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ArrayRef<CalleeSavedInfo> CSI,
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const TargetRegisterInfo *TRI) const override;
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bool
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restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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MutableArrayRef<CalleeSavedInfo> CSI,
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const TargetRegisterInfo *TRI) const override;
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bool allocateScavengingFrameIndexesNearIncomingSP(
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const MachineFunction &MF) const override;
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bool isSupportedStackID(TargetStackID::Value ID) const override;
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void processFunctionBeforeFrameFinalized(
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MachineFunction &MF,
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RegScavenger *RS = nullptr) const override;
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void processFunctionBeforeFrameIndicesReplaced(
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MachineFunction &MF, RegScavenger *RS = nullptr) const override;
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MachineBasicBlock::iterator
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eliminateCallFramePseudoInstr(MachineFunction &MF,
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MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI) const override;
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protected:
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bool hasFPImpl(const MachineFunction &MF) const override;
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private:
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void emitEntryFunctionFlatScratchInit(MachineFunction &MF,
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MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I,
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const DebugLoc &DL,
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Register ScratchWaveOffsetReg) const;
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Register getEntryFunctionReservedScratchRsrcReg(MachineFunction &MF) const;
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void emitEntryFunctionScratchRsrcRegSetup(
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MachineFunction &MF, MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I, const DebugLoc &DL,
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Register PreloadedPrivateBufferReg, Register ScratchRsrcReg,
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Register ScratchWaveOffsetReg) const;
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public:
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bool requiresStackPointerReference(const MachineFunction &MF) const;
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// Returns true if the function may need to reserve space on the stack for the
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// CWSR trap handler.
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bool mayReserveScratchForCWSR(const MachineFunction &MF) const;
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};
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} // end namespace llvm
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#endif // LLVM_LIB_TARGET_AMDGPU_SIFRAMELOWERING_H
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