Ulrich Weigand 9dd23b8433 [SystemZ] Test case formatting fixes ...

Fix systematically wrong whitespace from a prior automated change.

NFC.

llvm-svn: 337542

2018-07-20 12:12:10 +00:00

..

AArch64

[DAGCombiner] Add rotate-extract tests

2018-07-19 09:27:34 +00:00

AMDGPU

Reapply "AMDGPU: Fix handling of alignment padding in DAG argument lowering"

2018-07-20 09:05:08 +00:00

ARC

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ARM

ARM: switch armv7em MachO triple to hard-float defaults and libcalls.

2018-07-19 12:44:51 +00:00

AVR

[AVR] Set trackLivenessAfterRegAlloc

2018-06-11 14:46:48 +00:00

BPF

[DebugInfo] Add DILabel metadata and intrinsic llvm.dbg.label.

2018-05-09 02:40:45 +00:00

Generic

Implement strip.invariant.group

2018-07-02 04:49:30 +00:00

Hexagon

[Hexagon] Avoid introducing calls into coalesced range of HVX vector pairs

2018-07-13 23:42:29 +00:00

Inputs

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Lanai

Remove SETCCE use from Lanai's backend

2018-06-03 12:56:24 +00:00

Mips

[mips] Fix predicate for the MipsTruncIntFP pattern

2018-07-18 14:11:22 +00:00

MIR

[DebugInfo][X86] Add start-after flags to MIR tests

2018-07-12 14:36:48 +00:00

MSP430

Emit a left-shift instead of a power-of-two multiply for jump-tables

2018-05-16 08:58:26 +00:00

Nios2

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NVPTX

finish: [FileCheck] Add -allow-deprecated-dag-overlap to failing llvm tests

2018-07-11 20:31:51 +00:00

PowerPC

[Power9] Code Cleanup - Remove needsAggressiveScheduling()

2018-07-19 19:34:18 +00:00

RISCV

[RISCV] Add machine function pass to merge base + offset

2018-06-27 20:51:42 +00:00

SPARC

Revert "[Sparc] Use the IntPair reg class for r constraints with value type f64"

2018-07-18 10:05:30 +00:00

SystemZ

[SystemZ] Test case formatting fixes

2018-07-20 12:12:10 +00:00

Thumb

[CodeGen] Emit more precise AssertZext/AssertSext nodes.

2018-07-11 23:26:35 +00:00

Thumb2

[ARM] Treat cmn immediates as legal in isLegalICmpImmediate.

2018-07-10 23:44:37 +00:00

WebAssembly

[WebAssembly] Add missing -mattr=+exception-handling guards

2018-07-18 21:42:22 +00:00

WinCFGuard

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WinEH

[DebugInfo] Add DILabel metadata and intrinsic llvm.dbg.label.

2018-05-09 02:40:45 +00:00

X86

Revert "[LSV] Refactoring + supporting bitcasts to a type of different size"

2018-07-20 12:03:00 +00:00

XCore

[DAGCombiner] extend(ifpositive(X)) -> shift-right (not X)

2018-07-15 16:27:07 +00:00